AN414
... The major difference between the two parts is that the SCC2692 is CMOS, while the SCN2681 is NMOS. This means the SCC2692 draws significantly less power than the SCN2681. Another difference between the two parts is that the SCC2692 has used edge triggered latches for the configuration registers: MR1 ...
... The major difference between the two parts is that the SCC2692 is CMOS, while the SCN2681 is NMOS. This means the SCC2692 draws significantly less power than the SCN2681. Another difference between the two parts is that the SCC2692 has used edge triggered latches for the configuration registers: MR1 ...
SOLATRON™ Plus Three Phase Power Conditioners Catalog Pages
... 240 Vac Input, 240Y/139 Vac Output, 60 Hz 480 Vac Input, 240Y/139 Vac Output, 60 Hz 600 Vac Input, 240Y/139 Vac Output, 60 Hz ...
... 240 Vac Input, 240Y/139 Vac Output, 60 Hz 480 Vac Input, 240Y/139 Vac Output, 60 Hz 600 Vac Input, 240Y/139 Vac Output, 60 Hz ...
Dec 2005 Simplify High-Resolution Video Designs with Fixed-Gain Triple Multiplexers
... turns on when the IGBTIN pin is above 1.5V and turns off when the IGBTIN pin is below 0.3V. When the input is high, the driver draws a small amount of current to hold the gate high with a PNP. When the input is low, the driver has zero quiescent current. During transitions the driver is capable of d ...
... turns on when the IGBTIN pin is above 1.5V and turns off when the IGBTIN pin is below 0.3V. When the input is high, the driver draws a small amount of current to hold the gate high with a PNP. When the input is low, the driver has zero quiescent current. During transitions the driver is capable of d ...
JohnAnalog
... impedances with some combination of resistors and capacitors, one can obtain gain stages as well as more complicated pole/zero structures or bipolar shaping structures. The dc operating point of the amplifier is established by common mode feedback. The output nodes, OUTB (OUTA) are connected to the ...
... impedances with some combination of resistors and capacitors, one can obtain gain stages as well as more complicated pole/zero structures or bipolar shaping structures. The dc operating point of the amplifier is established by common mode feedback. The output nodes, OUTB (OUTA) are connected to the ...
MAX9010–MAX9013 SC70, 5ns, Low-Power, Single-Supply, Precision TTL Comparators General Description
... the existing output state is latched, and the input differential voltage has no further effect on the output state. ...
... the existing output state is latched, and the input differential voltage has no further effect on the output state. ...
AN-583 APPLICATION NOTE
... current shutdown connection. The board has a pull-up resistor installed so that if no connection is made at that point, the part operates in active mode. To enable the shutdown feature, connect the SD (Pin 1) on JP3 to ground. To perform an indepth analysis on the shutdown current, the pull-up resis ...
... current shutdown connection. The board has a pull-up resistor installed so that if no connection is made at that point, the part operates in active mode. To enable the shutdown feature, connect the SD (Pin 1) on JP3 to ground. To perform an indepth analysis on the shutdown current, the pull-up resis ...
Analog Signal Monitoring Option
... Monitoring Option For VERBATIM Automatic Dialing Remote Monitoring System ...
... Monitoring Option For VERBATIM Automatic Dialing Remote Monitoring System ...
UT54ACTS220 - Aeroflex Microelectronic Solutions
... 3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualific ...
... 3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualific ...
NTE2764 Integrated Circuit
... A verify should be performed on the programmed bits to determine that the data was correctly programmed. The program verify can be performed with CE and OE at low (0) levels and PGM at high (1) level. ...
... A verify should be performed on the programmed bits to determine that the data was correctly programmed. The program verify can be performed with CE and OE at low (0) levels and PGM at high (1) level. ...
BASIC Stamp I Application Notes 1
... a TTL inverter; its output does not have the required voltage swing. To transmit from a PC, you’ll need to add a diode and resistor ahead of the ’555 timer as shown in the schematic. These protect the timer from the negative voltage swings of the PC’s real RS-232 output. Modifications. I’m sure you’ ...
... a TTL inverter; its output does not have the required voltage swing. To transmit from a PC, you’ll need to add a diode and resistor ahead of the ’555 timer as shown in the schematic. These protect the timer from the negative voltage swings of the PC’s real RS-232 output. Modifications. I’m sure you’ ...
sdc-630/632/634* 10-, 12-, 14-bit synchro-to-digital or
... In the case of the RESOLVER version (RDC), the equation is: ...
... In the case of the RESOLVER version (RDC), the equation is: ...
Basic Digital Logic
... ◊ All circuits can actually be made using AND, OR and NOT gates if required. ...
... ◊ All circuits can actually be made using AND, OR and NOT gates if required. ...
AD557: 英文产品数据手册下载
... Settling time is specified for a positive-going full-scale step to ± 1/2 LSB. Negativegoing steps to zero are slower, but can be improved with an external pull-down. ...
... Settling time is specified for a positive-going full-scale step to ± 1/2 LSB. Negativegoing steps to zero are slower, but can be improved with an external pull-down. ...
Lab 3.8 Impedance of test instruments (p79)
... 2) Do the same for channel-1 of your oscilloscope in DC coupling mode with input scaling of 1 volt per division and a 100 Hz input signal from your signal generator. 3) How does the oscilloscope input impedance change when you increase the input signal frequency to 10 kHz? Your scope input can be mo ...
... 2) Do the same for channel-1 of your oscilloscope in DC coupling mode with input scaling of 1 volt per division and a 100 Hz input signal from your signal generator. 3) How does the oscilloscope input impedance change when you increase the input signal frequency to 10 kHz? Your scope input can be mo ...
ES1888 Audio Drive Product Brief
... adds 16-bit stereo sound and FM music synthesis to personal computers. It includes an embedded microprocessor, a 20-voice ESFM™ music synthesizer, 16-bit stereo wave ADC and DAC, 16bit stereo music DAC, MPU-401 UART mode serial port, dual game ports, hardware master volume control, two serial port i ...
... adds 16-bit stereo sound and FM music synthesis to personal computers. It includes an embedded microprocessor, a 20-voice ESFM™ music synthesizer, 16-bit stereo wave ADC and DAC, 16bit stereo music DAC, MPU-401 UART mode serial port, dual game ports, hardware master volume control, two serial port i ...
Xilinx FPGAs:Evolution and Revolution
... Any 4-input logic function Or 16-bit x 1 RAM Or 16-bit shift register ...
... Any 4-input logic function Or 16-bit x 1 RAM Or 16-bit shift register ...
比较器系列ADCMP606 数据手册DataSheet 下载
... lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Multiple high quality 0.01 μF bypass capacitors should be placed as close as possible to each of the VCCI and ...
... lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Multiple high quality 0.01 μF bypass capacitors should be placed as close as possible to each of the VCCI and ...
Circuit Note CN-0065
... By default, the DVCC pin on the AD5422 accepts a power supply of 2.7 V to 5.5 V. Alternatively, the DVCC SELECT pin can be used to connect an internal 4.5 V power supply to the DVCC pin for use as a digital power supply for other devices in the system or as a termination for pull-up resistors. Maxim ...
... By default, the DVCC pin on the AD5422 accepts a power supply of 2.7 V to 5.5 V. Alternatively, the DVCC SELECT pin can be used to connect an internal 4.5 V power supply to the DVCC pin for use as a digital power supply for other devices in the system or as a termination for pull-up resistors. Maxim ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.