HMC855LC5
... supporting broadband operation. All clock and data inputs to the HMC855LC5 are CML and terminated on-chip with 50 Ohms to the positive supply, GND, and may be DC or AC coupled. The differential outputs are source terminated to 50 Ohms and may also be AC or DC coupled. Outputs can be connected direct ...
... supporting broadband operation. All clock and data inputs to the HMC855LC5 are CML and terminated on-chip with 50 Ohms to the positive supply, GND, and may be DC or AC coupled. The differential outputs are source terminated to 50 Ohms and may also be AC or DC coupled. Outputs can be connected direct ...
... All the WRD_(M)P-3W Series have been tested according to the following recommended testing circuit before leaving factory. This series should be tested under load (see Figure 1). If you want to further decrease the input/output ripple, you can increase capacitance properly or choose capacitors with ...
Pulse Width Modulation Amplifiers
... maximum desired current. In current mode the required value of each RLIMIT is 2 times this value since the sense voltage is divided down by 2 (see Figure B). If RSHDN is used it will further divide down the sense voltage. The shutdown divider network will also have an effect on the filtering circuit ...
... maximum desired current. In current mode the required value of each RLIMIT is 2 times this value since the sense voltage is divided down by 2 (see Figure B). If RSHDN is used it will further divide down the sense voltage. The shutdown divider network will also have an effect on the filtering circuit ...
Integrated Synthesizer and VCO ADF4360-2 FEATURES
... Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Serial Clock Input. This serial clock is used to clock in the serial data to ...
... Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Serial Clock Input. This serial clock is used to clock in the serial data to ...
Multiplication, Division, Squaring, Square Rooting
... percent of full scale and includes XIN and YIN nonlinearities, feedback and scale factor error. To this must be added such application-dependent error terms as power supply rejection, common-mode rejection and temperature coefficients (although worst case error over temperature is specified for the ...
... percent of full scale and includes XIN and YIN nonlinearities, feedback and scale factor error. To this must be added such application-dependent error terms as power supply rejection, common-mode rejection and temperature coefficients (although worst case error over temperature is specified for the ...
Low voltage CMOS 3 to 8 line decoder with 5V tolerant inputs
... system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ...
... system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ...
74LCX257 Low Voltage Quad 2-Input Multiplexer with 5V Tolerant Inputs and Outputs 7
... outputs. It selects four bits of data from two sources under control of a Common Data Select input. When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in true (non inverted) form. The ...
... outputs. It selects four bits of data from two sources under control of a Common Data Select input. When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in true (non inverted) form. The ...
1 . General Description
... The power supply shall maintain voltage regulation within the Specified limits in paragraph 2-2-1 for at least 16 milliseconds after Lost of input voltage measure at 220VAC and at maximum output load. ...
... The power supply shall maintain voltage regulation within the Specified limits in paragraph 2-2-1 for at least 16 milliseconds after Lost of input voltage measure at 220VAC and at maximum output load. ...
Measurement of large pulses from reset time
... Measurement performed at Padova with HPGe detector (courtesy of D. Bazzacco and R. Isocrate) Zocca, ”A new low-noise preamplifier for g-ray sensors with smart device for large signal management”, Laurea Degree Thesis, University of Milano, October 2004 (in Italian). See http://topserver.mi.infn.it/m ...
... Measurement performed at Padova with HPGe detector (courtesy of D. Bazzacco and R. Isocrate) Zocca, ”A new low-noise preamplifier for g-ray sensors with smart device for large signal management”, Laurea Degree Thesis, University of Milano, October 2004 (in Italian). See http://topserver.mi.infn.it/m ...
UM3222E,UM3232E High ESD-Protected, Low Power, 3.3V to 5.5V
... voltages of +5.5V (doubling charge pump) and -5.5V (inverting charge pump) over the +3.0V to +5.5V VCC range. The charge pump operates in discontinuous mode; if the output voltages are less than 5.5V, the charge pump is enabled, and if the output voltages exceed 5.5V, the charge pump is disabled. Ea ...
... voltages of +5.5V (doubling charge pump) and -5.5V (inverting charge pump) over the +3.0V to +5.5V VCC range. The charge pump operates in discontinuous mode; if the output voltages are less than 5.5V, the charge pump is enabled, and if the output voltages exceed 5.5V, the charge pump is disabled. Ea ...
doc
... intended for high-speed digitisation, bypassing the peak-hold/mux stages. It is possible to resolve closely separated pulses on a single channel, where the separation might be too small for the peak-hold. These outputs have high-speed buffers (~10ns rise-time) in order to retain information about th ...
... intended for high-speed digitisation, bypassing the peak-hold/mux stages. It is possible to resolve closely separated pulses on a single channel, where the separation might be too small for the peak-hold. These outputs have high-speed buffers (~10ns rise-time) in order to retain information about th ...
Operational Amplifiers
... What forces the OA to behave so „reasonably“? The negative feedback always sets the output voltage to such a value that the voltage between the inputs is zero. ...
... What forces the OA to behave so „reasonably“? The negative feedback always sets the output voltage to such a value that the voltage between the inputs is zero. ...
report
... grown; the reduction of power dissipation is a crucial factor in IC design . In many applications, the power consumption of the IC clock system is one of the main sources of chip power dissipation. This is due to the high switching activity and the heavy capacitive loading of the clock network. Cons ...
... grown; the reduction of power dissipation is a crucial factor in IC design . In many applications, the power consumption of the IC clock system is one of the main sources of chip power dissipation. This is due to the high switching activity and the heavy capacitive loading of the clock network. Cons ...
DM74LS373 • DM74LS374 3-STATE Octal D
... The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-t ...
... The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-t ...
CMOS Schmitt Trigger Test Circuit
... • A type of comparator. • A comparator is an electronic circuit whose output state changes when its input reaches a certain value. • A comparator’s output state will change at the same input value whether the input voltage is increasing or decreasing. • A noisy signal can cause the output to change ...
... • A type of comparator. • A comparator is an electronic circuit whose output state changes when its input reaches a certain value. • A comparator’s output state will change at the same input value whether the input voltage is increasing or decreasing. • A noisy signal can cause the output to change ...
2.2 - KTH
... Combines local delay with the worst-case incoming delay value. Nonunate timing arcs are present in logic functions whose output value change cannot be predicted by the direction of the change on the input value. An example is an XOR gate. • Accuracy of estimates is critical • Intrinsic Delays are ac ...
... Combines local delay with the worst-case incoming delay value. Nonunate timing arcs are present in logic functions whose output value change cannot be predicted by the direction of the change on the input value. An example is an XOR gate. • Accuracy of estimates is critical • Intrinsic Delays are ac ...
NTE7142 - NTE Electronics Inc
... Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the ...
... Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the ...
74373
... The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-t ...
... The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-t ...
ADC1205 ADC1225 12-Bit Plus Sign MuP
... The ADC 1225 makes all thirteen bits of the conversion result available in parallel. Taking CS and RD low enables the TRI-STATEÉ output buffers. The conversion result is represented in 2’s complement format. The ADC1205 makes the conversion result available in two eight-bit bytes. The output format ...
... The ADC 1225 makes all thirteen bits of the conversion result available in parallel. Taking CS and RD low enables the TRI-STATEÉ output buffers. The conversion result is represented in 2’s complement format. The ADC1205 makes the conversion result available in two eight-bit bytes. The output format ...
Frequently Asked Questions FAQ
... Typically the SCR-DI is best used between your bass and the input of your amplifier but it can also be used in an effects loop. ...
... Typically the SCR-DI is best used between your bass and the input of your amplifier but it can also be used in an effects loop. ...
MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer General Description
... parallel clock frequency of 3MHz to 35MHz, deserializing video data to the RGB_OUT[17:0] outputs when the data enable output DE_OUT is high, or control data to the CNTL_OUT[8:0] outputs when DE_OUT is low. The video phase words are decoded using 2 overhead bits, EN0 and EN1. Control phase words are ...
... parallel clock frequency of 3MHz to 35MHz, deserializing video data to the RGB_OUT[17:0] outputs when the data enable output DE_OUT is high, or control data to the CNTL_OUT[8:0] outputs when DE_OUT is low. The video phase words are decoded using 2 overhead bits, EN0 and EN1. Control phase words are ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.