AD9863 - Analog Devices
... (for example, coarse and fine gain control and offset control for channel matching) and the ADC path (for example, the internal duty cycle stabilizer and twos complement data format). The AD9863 is packaged in a 64-lead LFCSP (low profile, fine pitched, chip scale package). The 64-lead LFCSP footpri ...
... (for example, coarse and fine gain control and offset control for channel matching) and the ADC path (for example, the internal duty cycle stabilizer and twos complement data format). The AD9863 is packaged in a 64-lead LFCSP (low profile, fine pitched, chip scale package). The 64-lead LFCSP footpri ...
MAX9209/MAX9213 Programmable DC-Balanced 21-Bit Serializers General Description
... The MAX9209 operates at a parallel clock frequency of 8MHz to 34MHz in DC-balanced mode and 10MHz to 40MHz in non-DC-balanced mode. The MAX9213 operates at a parallel clock frequency of 16MHz to 66MHz in DC-balanced mode and 20MHz to 85MHz in nonDC-balanced mode. DC-balanced or non-DC-balanced opera ...
... The MAX9209 operates at a parallel clock frequency of 8MHz to 34MHz in DC-balanced mode and 10MHz to 40MHz in non-DC-balanced mode. The MAX9213 operates at a parallel clock frequency of 16MHz to 66MHz in DC-balanced mode and 20MHz to 85MHz in nonDC-balanced mode. DC-balanced or non-DC-balanced opera ...
AN-104 Noise Specs Confusing (Rev. C)
... This all means that it does not make sense to tamper with the Rgen of existing signal sources in an attempt to make Rgen = ROPT. Especially, do not add series resistance to a source for this purpose. It does make sense to adjust Rgen in transformer coupled circuits by manipulating turns ratio or to ...
... This all means that it does not make sense to tamper with the Rgen of existing signal sources in an attempt to make Rgen = ROPT. Especially, do not add series resistance to a source for this purpose. It does make sense to adjust Rgen in transformer coupled circuits by manipulating turns ratio or to ...
MAX1132/MAX1133 16-Bit ADC, 200ksps, 5V Single-Supply with Reference General Description
... external clock for calibration by setting the INT/EXT bit in the Control Byte. Calibrate the MAX1132/MAX1133 with the clock used for performing conversions. Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1132/ MAX1133’s calibration circuitry. However, ...
... external clock for calibration by setting the INT/EXT bit in the Control Byte. Calibrate the MAX1132/MAX1133 with the clock used for performing conversions. Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1132/ MAX1133’s calibration circuitry. However, ...
Metacom SCADA Communications Systems Metacom MC402
... If Mode = 3 then the device is not on GPRS due to a GPRS problem in the area. The MC402 will automatically detect GPRS problems and set the mode=3 and try to reconnect to GPRS regularly (Default is 15 Minutes). You should wait for 15 minutes and try again. Configuration problem on the Base Router an ...
... If Mode = 3 then the device is not on GPRS due to a GPRS problem in the area. The MC402 will automatically detect GPRS problems and set the mode=3 and try to reconnect to GPRS regularly (Default is 15 Minutes). You should wait for 15 minutes and try again. Configuration problem on the Base Router an ...
FMS6501A 12x9 Video Switch Matrix with Input Clamp, Input Bias
... With AC-coupled inputs, the FMS6501A uses a simple clamp rather than a full DC-restore circuit. For video signals with and without sync (Y, CV, R, G, B); the lowest voltage at the output pins is clamped to ~300 mV above ground when the 6dB gain setting is selected. If symmetric AC-coupled input sign ...
... With AC-coupled inputs, the FMS6501A uses a simple clamp rather than a full DC-restore circuit. For video signals with and without sync (Y, CV, R, G, B); the lowest voltage at the output pins is clamped to ~300 mV above ground when the 6dB gain setting is selected. If symmetric AC-coupled input sign ...
MAX1142/MAX1143 14-Bit ADC, 200ksps, +5V Single-Supply with Reference General Description
... Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1142/ MAX1143’s calibration circuitry. However, because the magnitude of the offset produced by a synchronous signal depends on the signal’s shape, recalibration may be appropriate if the shape or relative ...
... Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1142/ MAX1143’s calibration circuitry. However, because the magnitude of the offset produced by a synchronous signal depends on the signal’s shape, recalibration may be appropriate if the shape or relative ...
MAX197 Multi-Range (±10V, ±5V, +10V, +5V), _______________General Description
... The MAX197 multi-range, 12-bit data-acquisition system (DAS) requires only a single +5V supply for operation, yet accepts signals at its analog inputs that may span both above the power-supply rail and below ground. This system provides 8 analog input channels that are independently software program ...
... The MAX197 multi-range, 12-bit data-acquisition system (DAS) requires only a single +5V supply for operation, yet accepts signals at its analog inputs that may span both above the power-supply rail and below ground. This system provides 8 analog input channels that are independently software program ...
IQ ECO - INTEGRATED cONTROL tECHNOLOGIES, LLC
... PC is removed. The sCNC’s address should be set non-zero if it is likely that software tools could be connected to more than one IQeco simultaneously on the same MS/TP trunk. (This will prevent an address clash at address 125). It can be changed using the IQTool monitor task IQecoDiagnostics_Strateg ...
... PC is removed. The sCNC’s address should be set non-zero if it is likely that software tools could be connected to more than one IQeco simultaneously on the same MS/TP trunk. (This will prevent an address clash at address 125). It can be changed using the IQTool monitor task IQecoDiagnostics_Strateg ...
Xilinx XAPP756 Transmitting DDR Data Between LVDS and
... kinds of devices. Additionally, a design transmitting data from LVDS to CML using Xilinx technology is available. ...
... kinds of devices. Additionally, a design transmitting data from LVDS to CML using Xilinx technology is available. ...
TJF1052i CAN 1. General description
... Safety: Isolation is required for safety reasons, eg. to protect humans from electric shock or to prevent the electronics being damaged by high voltages. Signal integrity: The isolator uses proprietary capacitive isolation technology to transmit and receive CAN signals. This technology enables more ...
... Safety: Isolation is required for safety reasons, eg. to protect humans from electric shock or to prevent the electronics being damaged by high voltages. Signal integrity: The isolator uses proprietary capacitive isolation technology to transmit and receive CAN signals. This technology enables more ...
MAX11152 18-Bit, 500ksps, +5V Unipolar Input, SAR ADC, in Tiny 10-Pin µMAX
... Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Expo ...
... Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Expo ...
SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs ADAU1401A
... Qualified for automotive applications ...
... Qualified for automotive applications ...
AD9755 数据手册DataSheet 下载
... The DAC utilizes a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Differential current outputs support single-ended or differential applications. The differential outputs each provide a nominal full-scale c ...
... The DAC utilizes a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Differential current outputs support single-ended or differential applications. The differential outputs each provide a nominal full-scale c ...
![Spartan-3 FPGA Family - start [kondor.etf.rs]](http://s1.studyres.com/store/data/006500847_1-986be0be37a885f32642aebba00b9157-300x300.png)
Spartan-3 FPGA Family - start [kondor.etf.rs]
... option. Any inverter placed on these paths is automatically absorbed into the IOB. ...
... option. Any inverter placed on these paths is automatically absorbed into the IOB. ...
Super-Positioning of Voltage Sources for Fast Assessment of Wide
... matrices must be copied to a new memory location for every 4 processors. This might explain why the speed-up saturates around 12 processors for the given problem. The wall-time passed during execution on 12 processors is 1.2s which is still not quite satisfactory if the equivalents are to be used in ...
... matrices must be copied to a new memory location for every 4 processors. This might explain why the speed-up saturates around 12 processors for the given problem. The wall-time passed during execution on 12 processors is 1.2s which is still not quite satisfactory if the equivalents are to be used in ...
SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs ADAU1401A
... Qualified for automotive applications ...
... Qualified for automotive applications ...
AD9751 数据手册DataSheet 下载
... The DAC utilizes a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Differential current outputs support single-ended or differential applications. The differential outputs each provide a nominal full-scale c ...
... The DAC utilizes a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Differential current outputs support single-ended or differential applications. The differential outputs each provide a nominal full-scale c ...
Welch Allyn Pediatric/Infant Scale Service Manual
... The output signal from the load cells is applied to the protection network consisting of diodes CR4/CR5/CR6/CR7. These diodes prevent destructive high voltages caused by static discharges from damaging U4. A high frequency filter, formed by L1/L2/C9, C10 couples the weight signal to the input of U4. ...
... The output signal from the load cells is applied to the protection network consisting of diodes CR4/CR5/CR6/CR7. These diodes prevent destructive high voltages caused by static discharges from damaging U4. A high frequency filter, formed by L1/L2/C9, C10 couples the weight signal to the input of U4. ...
TS3DV520E 5-Channel Differential 10:20 Multiplexer Switch (Rev. B)
... The TS3DV520E is a 20-bit to 10-bit multiplexer/demultiplexer digital video switch with a single select (SEL) input. SEL controls the data path of the multiplexer/demultiplexer. The device provides five differential channels for digital video signal switching. This device provides low and flat ON-st ...
... The TS3DV520E is a 20-bit to 10-bit multiplexer/demultiplexer digital video switch with a single select (SEL) input. SEL controls the data path of the multiplexer/demultiplexer. The device provides five differential channels for digital video signal switching. This device provides low and flat ON-st ...
AD9649 - Analog Devices
... A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO, data output (D13 to D0) timing and offset adjustments, and voltage reference modes. The AD9649 is packaged in a 32-lead RoHS-compliant LFCS ...
... A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO, data output (D13 to D0) timing and offset adjustments, and voltage reference modes. The AD9649 is packaged in a 32-lead RoHS-compliant LFCS ...
chapter 4: signal to noise ratio
... moving average and the loss and/or distortion of vital information is comparatively limited. ...
... moving average and the loss and/or distortion of vital information is comparatively limited. ...
AD5292-EP: 1024-Position, Digital Potentiometer with Maximum ±1% R-Tolerance Error and 20-TP Memory
... Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC following the 16th ...
... Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC following the 16th ...
![Modified Derivative Superposition Method for Linearizing FET Low-Noise Amplifiers , Fellow, IEEE [4]–[7].](http://s1.studyres.com/store/data/008933224_1-2d88e15357b12c718a7f6ce155a9c9cc-300x300.png)
Modified Derivative Superposition Method for Linearizing FET Low-Noise Amplifiers , Fellow, IEEE [4]–[7].
... a simultaneous noise-power input match leading to a higher NF. This NF increase comes in addition to an intrinsically higher NF of a composite FET in comparison with a single FET (higher by 0.6 dB, as reported in [10]). This NF increase due to replacing a single FET by a composite FET in the DS meth ...
... a simultaneous noise-power input match leading to a higher NF. This NF increase comes in addition to an intrinsically higher NF of a composite FET in comparison with a single FET (higher by 0.6 dB, as reported in [10]). This NF increase due to replacing a single FET by a composite FET in the DS meth ...