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Lecture 10
Metal-Oxide-Semiconductor (MOS)
Field-Effect Transistors (FET)
MOSFET
Bias Analysis
Goals
• Investigate circuits that bias transistors into different
operating regions.
•
•
•
•
Two Supplies Biasing
Four Resistor Biasing
Two Resistor Biasing
Biasing using Current Mirror
• Understand Bias Point Stability
• Investigate DC Analysis for P-Channel Transistor
Bias Analysis Approach
• Assume an operation region (generally the saturation
region)
• Use circuit analysis to find VGS
• Use VGS to calculate ID, and ID to find VDS
• Check validity of operation region assumptions
• Change assumptions and analyze again if required.
NOTE :An enhancement-mode device with VDS = VGS is
always in saturation
Bias Analysis of n-channel
MOSFET
Check VGS
we start the analysis by
assuming certain
operating region
VGS> Vt
VGS< VTN
VDS < VGS –VTN
Triode region
Cutoff region
iD=0
iD 
1
W
K n ' ( )[ 2(VGS  VTN )VDS ]
2
L
VDS > VGS –VTN
Sat. region
iD 
1
W
K ' ( )(VGS  VTN ) 2
2
L
Example-1
Biasing using two
voltage supplies for
gate and drain
terminal
Example 2 ( Biasing in Triode Region)
Also
 I ( R  R ) V
DD D D S
DS
4  1600I V
D DS
V
 2.19V
DS
V
But VDS<VGS-VTN. Hence, saturation
region assumption is incorrect
Using triode region equation,
Assumption: IG=IB=0, transistor
is saturated (since VDS= VGS)
Analysis: VGS=VDD=4 V
I  250 μA (4 1)2  1.13mA
D 2 V2
V
μA
250
4 V
 1600
(4 1 DS )V
DS
DS
2 V2
2
V
DS
 2.3V and ID=1.06 mA
VDS<VGS-VTN, transistor is in triode region
Q-pt:(1.06 mA, 2.3 V)
Four-Resistor and Two-Resistor Biasing
• Provide excellent bias for transistors in discrete circuits.
• Stabilize bias point with respect to device parameter and
temperature variations using negative feedback.
• Use single voltage source to supply both gate-bias voltage
and drain current.
• Generally used to bias transistors in saturation region.
• Two-resistor biasing uses lesser components that fourresistor biasing and also isolates drain and gate terminals
Bias Analysis: Example3 (Four-Resistor
Biasing)
Assumption: Transistor is saturated,
IG=IB=0
Analysis: First, simplify circuit, split
VDD into two equal-valued sources and
apply Thevenin transformation to find
VEQ and REQ for gate-bias voltage
Problem: Find Q-pt (ID, VDS)
Approach: Assume operation
region, find Q-point, check to see if
result is consistent with operation
region
Bias Analysis: Example 3 (Four-Resistor
Biasing) (contd.)
V 2  0.05V  7.21  0
GS
GS
V  2.71V,2.66V
GS
Since VGS<VTN for VGS= -2.71 V
and MOSFET will be cut-off,
Since IG=0,
V
V  I R
EQ GS D S
Kn R 
2
S V V 
V
V 


EQ GS
2  GS TN 



 25 10  6  3.9 104 

4 V  
GS
V  2.66V and ID= 34.4 mA
GS
Also, VDD  I D ( RD  RS ) VDS


2

 V

 GS
V
1

2
DS
 6.08V
VDS>VGS-VTN. Hence
saturation region assumption is
correct.
Q-pt: (34.4 mA, 6.08 V) with
VGS= 2.66 V
Two Resistor Biasing
Biasing the MOSFET using a large
drain-to-gate feedback resistance, RG.
VDD> Vt  MOS is ON and always in saturation
(diode connected transistor)
VD  VG
VDS  VGS
1
iD  K ' (W / L)(VDS  Vt ) 2
2
VDS  Vdd  iD RD
Bias Analysis: Example 4 (Two-Resistor
Biasing)
Kn R 
2
D V V 
V V



GS DD
2  GS TN 



 2.6 10 4 104 
V
GS

 3.3  


2

 V

 GS
V  0.769V,2.00V
GS
Since VGS<VTN for VGS= -0.769 V
and MOSFET will be cut-off,
Assumption: IG=IB=0, transistor is
saturated (since VDS= VGS)
Analysis:
V V
I R
DS DD D D
V  2.00V and ID= 130 mA
GS
VDS>VGS-VTN. Hence saturation
region assumption is correct.
Q-pt: (130 mA, 2.00 V)
2
1

Additional Biasing Circuits_2
Using constant current source
i D  iS  I
1
I  ( K 'W / L)(VGS  Vt ) 2
2
VGS  VG  VS , VG  0
1
I  ( K 'W / L)( VS  Vt ) 2
2
2I
Vs 
 Vt
K 'W / L
How to implement a current source
(Current mirrors)
For Q1
VDS  VGS
diode connected transisto r
1
K 'W / L(VGS1  Vt )2
2
2 I D1
VGS1  Vt 
...................(1)
K 'W / L
VDS1  VGS1  VDD  I ref R............(2)
I ref  I D1 
I ref is given
For Q2
VGS 2  VGS1
2 I DS 2

K ' (W / L) 2
2 I DS1
K ' (W / L)1
I ref
I DS 2

(W / L) 2 (W / L)1
N-branch current mirror
Iref
I1
I2
(W/L)1
(W/L)2
In
W/L
(W/L)n
In
Iref
I1
I2



(W / L) (W / L) 1 (W / L) 2 (W / L) n
n-channel and P-Channel MOSFETs
DC –Analysis of P-channel MOS
Note: The direction of
current is out of the
drain for a PMOS
Bias Analysis: Example 5 (Two-Resistor
biasing for PMOS Transistor)
Also 15V  (220kΩ) I D VDS  0
2
15V  (220kΩ) 50 μA V  2  V  0
GS
2 V2  GS 
V  0.369V,3.45V
GS
Since VGS= -0.369 V is less than VTP= -2
V, VGS = -3.45 V
Assumption: IG=IB=0, transistor
is saturated (since VDS= VGS)
Analysis:
V  (470kΩ) I V
0
GS
G DS
ID = 52.5 mA and VGS = -3.45 V
V
DS
V
GS
V
TP
Hence saturation assumption is correct.
Q-pt: (52.5 mA, -3.45 V)
Example
The circuit below uses a p-channel
enhancement MOSFET with
k’(W/L) = 2 mA/V2 and Vt = -1 V.
Find the value for R that produces
V0 = 10 V.
Modifications to Drain Current Equations
Channel-Length Modulation
Increasing vDS beyond vDSsat causes the
channel pinch-off point to move slightly
away from the drain, thus reducing the
effective channel length (by ΔL).
Effect of vDS on iD in the saturation region. The
MOSFET parameter VA depends on the process
technology and, for a given process, is
proportional to the channel length L.
It can be called; channel length modulation (λ), or Early voltage (VA)
Example
• A saturated MOSFET is operated with a constant vGS. The
drain current, iD, is found to be 2 mA for vDS = 4 V and 2.2
mA for vDS = 8 V. Find the values of VA, λ and ro.
Including the effect of Channel Length Modulation in the
MOSFET model
(Valid in the Saturation region)
1
W
K ' ( )(VGS  Vt ) 2 (1  VDS )
2
L
1
V
Output
ro 
 A
I D I D
iD 
W
 1

ro   K ' ( )(VGS  Vt ) 2 
L
 2

1
resistance
Bias-Point Stability for MOS Amplifiers
(source degeneration)
iD
iD
Variations
in K’(W/L)
VG
Rs
RS
Rs
VGS=VG-iDRS
Large Rs  stable bias
point but requires large
supply voltage
Rs is called degeneration
resistance
VGS
Vt1
Vt2
Variation in Vt