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Last Class: Introduction
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Operating system =
interface between
user & architecture
Importance of OS
OS history:
Change is only
constant
User-level Applications
virtual machine interface
Operating System
physical machine interface
Hardware
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Today:
OS & Computer Architecture
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Modern OS Functionality (brief review)
Architecture Basics
Hardware Support for OS Features
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Modern OS Functionality
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CPU management
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Concurrency (multiple simultaneous activities)
How to achieve it? How to schedule? How to
avoid conflict?
Memory management
Disk management
I/O Device Management
Advanced: support for
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distributed systems & networks
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Operating Systems = Governments
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Infinite RAM, CPU
Protect users from each other: safety
Fair allocation of resources
To each according to his needs
Manage resources efficiently
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Canonical System Hardware
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CPU: Processor to perform
actual computations
I/O devices: terminal,
disks, video, printer…
Memory: data & programs
System Bus:
Communication channel
between above
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Services & Hardware Support
OS Service
Hardware Support
Protection
Kernel/User Mode
Protected Instructions
Base & Limit Registers
Interrupts
Interrupt Vectors
System Calls
Trap Instructions
I/O
Interrupts, Memory-Mapping
Synchronization
Atomic Instructions
Virtual Memory
Translation Lookaside Buffers
Scheduling
Timer
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Protection
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OS protects users from each other
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Users cannot read or write other user’s memory
Protects self from users
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Safe from errant or malicious users
Code & data protected
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Kernel Mode:
Privileged Instructions
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CPU provides “kernel” mode restricted to OS
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Privileged instructions & registers:
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Inaccessible to ordinary users
Kernel = core of operating system
Direct access to I/O
Modify page table pointers, TLB
Enable & disable interrupts
Halt the machine, etc.
Indicated by status bit in protected CPU register
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Protecting Memory:
Base and Limit Registers
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Hardware support to protect
memory regions
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CPU checks each reference
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Loaded by OS before starting
program
Instruction & data addresses
Ensures reference in range
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Hardware Support
OS Service
Hardware Support
Protection
Kernel/User Mode
Protected Instructions
Base & Limit Registers
Interrupts
Interrupt Vectors
Traps
Trap Instructions
I/O
Interrupts, Memory-Mapping
Synchronization
Atomic Instructions
Virtual Memory
Translation Lookaside Buffers
Scheduling
Timer
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Interrupts
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Interrupt: Let CPU work while doing I/O
I/O is s..l..o..w for CPU
 I/O device has own processor
 When finished, device sends interrupt on bus
 CPU “handles” interrupt
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CPU Interrupt Handling
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Handling interrupts: relatively expensive
CPU must:
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Save hardware state (why?)
 Registers, program counter
Disable interrupts (why?)
Invoke via in-memory interrupt vector (like trap vector, soon)
Enable interrupts
Restore hardware state
Continue execution of interrupted
process
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Hardware Support
OS Service
Hardware Support
Protection
Kernel/User Mode
Protected Instructions
Base & Limit Registers
Interrupts
Interrupt Vectors
Traps
Trap Instructions
I/O
Interrupt vectors, MemoryMapping
Synchronization
Atomic Instructions
Virtual Memory
Translation Lookaside Buffers
Scheduling
Timer
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Traps
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Special conditions detected by architecture
 E.g.: page fault, write to read-only page, overflow,
system call
On detecting trap, hardware must:
 Save process state (PC, stack, etc.)
 Transfer control to trap handler (in OS)
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CPU indexes trap vector by trap number
Jumps to address
Restore process state and resume
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Hardware Support
OS Service
Hardware Support
Protection
Kernel/User Mode
Protected Instructions
Base & Limit Registers
Interrupts
Interrupt Vectors
Traps
Trap Instructions
I/O
Interrupt vectors, MemoryMapping
Synchronization
Atomic Instructions
Virtual Memory
Translation Lookaside Buffers
Scheduling
Timer
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Memory-Mapped I/O
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Direct access to I/O controller through memory
Reserve area of memory for communication
with device (“DMA”)
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Video RAM:
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CPU writes frame buffer
Video card displays it
Fast and convenient
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Hardware Support
OS Service
Hardware Support
Protection
Kernel/User Mode
Protected Instructions
Base & Limit Registers
Interrupts
Interrupt Vectors
System Calls
Trap Instructions
I/O
Interrupt vectors, MemoryMapping
Synchronization
Atomic Instructions
Virtual Memory
Translation Lookaside Buffers
Scheduling
Timer
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Synchronization
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How can OS synchronize concurrent
processes?
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E.g., multiple threads, processes & interrupts,
DMA
CPU must provide mechanism for atomicity
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Series of instructions that execute as one or not
at all
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Synchronization: How-To
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One approach:
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Advantages:
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Disable interrupts
Perform action
Enable interrupts
Requires no hardware support
Conceptually simple
Disadvantages:
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Could cause starvation
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Synchronization: How-To, II
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Modern approach: atomic instructions
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Small set of instructions that cannot be interrupted
Examples:
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Test-and-set (“TST”)
if word contains given value, set to new value
Compare-and-swap (“CAS”)
if word equals value, swap old value with new
Intel: LOCK prefix (XCHG, ADD, DEC, etc.)
Used to implement locks
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Hardware Support
OS Service
Hardware Support
Protection
Kernel/User Mode
Protected Instructions
Base & Limit Registers
Interrupts
Interrupt Vectors
System Calls
Trap Instructions
I/O
Interrupt vectors, MemoryMapping
Synchronization
Atomic Instructions
Virtual Memory
Translation Lookaside Buffers
Scheduling
Timer
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Virtual Memory
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Provides illusion of complete access to RAM
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OS loads pages from disk as needed
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All addresses translated from physical addresses into
virtual addresses
Keeps track of which pages are in memory (“in core”)
and which are on disk
Many benefits, including:
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Allows users to run programs without loading entire
program into RAM
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May not fit in entirety (think MS Office)
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Translation Lookaside Buffer
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First virtual memory systems performed
address translation in software
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On every memory access! (s..l..o..w..)
Modern CPUs contain hardware to do this:
the TLB
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Hash-based scheme
Maps virtual addresses to physical addresses
Fast, fully-associative cache
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Hardware Support
OS Service
Hardware Support
Protection
Kernel/User Mode
Protected Instructions
Base & Limit Registers
Interrupts
Interrupt Vectors
System Calls
Trap Instructions
I/O
Interrupt vectors, MemoryMapping
Synchronization
Atomic Instructions
Virtual Memory
Translation Lookaside Buffers
Scheduling
Timer
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Scheduling & Timers
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OS needs timers for:
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Time of day
CPU scheduling
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Fairness: limited quantum (e.g., 100ms) for each task
When quantum expires, switch processes
Uses interrupt vector
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Summary
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OS relies on hardware for many services
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Protection
Interrupts
Traps
Synchronization
Virtual memory
Timers
Otherwise impossible or impractically slow in
software
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From Architecture to OS to User
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Architectural resources, OS services, user
abstractions
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