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Altera EPLD: Synchronous vs. Asynchronous Mode Altera EPLDs contain 10s-100s of independently programmed macrocells Global CLK Personalized by EPROM bits: Clk MUX Synchronous Mode 1 Flipflop controlled by global clock signal OE/Local CLK Q EPROM Cell Global CLK Clk MUX local signal computes output enable Asynchronous Mode 1 OE/Local CLK Q EPROM Cell Flipflop controlled by locally generated clock signal + Seq Logic: could be D, T positive or negative edge triggered + product term to implement clear function CS 150 â Fall 2007 - Lec #27: FPGA Evolution â 15
