Download MC68HC11 Instruction Set

Overview
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68HC11 instruction set
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MC68HC11
Instruction Set
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A quick look at the programming procedure
The programmer's model
Instruction types and formats
Addressing modes
A tour of the instruction set
Readings for instruction set:
– Spasov, Chap. 2 and Appendix A
– HC11 Reference Manual, Appendix A
– HC11 Programming Reference Guide
EE 4535 – Packet 3
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EE 4535 – Packet 3
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Looking ahead at the
programming procedure:
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Soon you'll write programs in
assembly language for the HC11
Here's a super simple example program:
File name: try1.asm
TLOOP:
; Super simple test program
ORG $B600
TLOOP: INCA
INCB
JMP TLOOP
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AS11.exe
Before the HC11 can run this program,
– the assembly-language code needs to be
converted to machine language, and
– the machine-language code needs to be
transferred to the HC11's memory
Here is the machine code that results from
the assembly-lang. program given above
address
$B600
$B601
$B602
$B603
$B604
EE 4535 – Packet 3
; Super simple test program
ORG $B600
INCA
INCB
JMP TLOOP
File name: try1.s19
S108B6004C5C7EB60065
S9030000FC
File name: try1.lst
Assembler release TER_2.0 ver
(c) Motorola (free ware)
0001
. . .
DevHC11.exe
HC11 memory
contents
01001100
01011100
01111110
10110110
00000000
$B600
$B601
$B602
$B603
$B604
3
EE 4535 – Packet 3
...
01001100
01011100
01111110
10110110
00000000
...
4
2
Putting it all together
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Programmer's model
try1.asm is a source file
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– It is created by you, the programmer,
using a text editor on your PC
– Format: HC11 assembly language (ASCII text)
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try1.lst is a listing file
–
–
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– It is created by AS11.exe, the assembler/linker
that runs on your PC
– (You'll probably run AS11.exe from DevHC11.exe)
– Its purpose of the file is to help you debug the program
– Format: ASCII text
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try1.s19 is an object file
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– It is created by AS11.exe, the assembler/linker
– Its purpose is to specify what bytes should be downloaded
to the HC11, and to what locations in HC11 memory
– Format: Motorola S-record (ASCII text)
– Sometimes this is called a hex file
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What features of the processor are most
important to the assembly-language
programmer?
Register set
Memory organization
Instruction set
Addressing modes
Here is the register set (again):
The object file is converted to executable machine code
– The machine code is created by DevHC11.exe, the
development environment that runs on your PC
– Its purpose is to provide instructions and data to the HC11
– Format: HC11 machine language (binary)
– Sometimes this is called the binary code
– The machine code is transferred to the HC11 through the
coordinated efforts of DevHC11.exe (running on your PC)
and the Buffalo monitor program (running on the HC11)
EE 4535 – Packet 3
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EE 4535 – Packet 3
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3
Accumulators
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– A:
8-bit general purpose accumulator
– B:
8-bit general purpose accumulator
– D:
Double accumulator (concatenation of A
and B for 16-bit operations)
� Most operations can be done using either
accumulator A or B
�Stack may be anywhere in the 64 Kbyte address
space
�The stack grows downward in memory
(i.e., a push decrements SP)
– X:
16-bit index register
– Y:
16-bit index register
� X and Y are used for indexed addressing
� X is preferred, usually, because addressing with Y is
slower and takes 1 extra byte of object code than
with X
� Operations on index registers:
» Simple operations (INC, DEC, and ADD from B)
can be performed
» More complex operations are done by
exchanging the index register and the D register,
doing some computation, and then exchanging
the values again
» X or Y is often loaded with the base address of
the I/O register address space ($1000)
EE 4535 – Packet 3
$0000
$0000
...
Index registers
SP
SP
PSHA
data_2
data_1
...
data_1
$FFFF
7
EE 4535 – Packet 3
...
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SP: 16-bit stack pointer
...
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$FFFF
8
4
Overview of the 68HC11
instruction set
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PC: 16-bit Program Counter
CCR: 8-bit Condition Code Register
– H, N, Z, V, C: Arithmetic status bits
» N:
Negative result
» Z:
Zero result
» V:
Overflow result
» C:
Carry out from operation
» H:
Carry from low nibble (4 bits) of
accumulator
– S: Stop bit disabled
» =1 disables STOP instruction
» =1 after processor reset
– I: Interrupt mask
» =1 masks all maskable interrupts (not XIRQ)
» =1 after processor reset
– X: XIRQ interrupt mask
» =1 masks XIRQ
» =1 after processor reset (must be cleared just
after reset)
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– Data transfers: instructions that move data to
and between registers
– Logical: instructions that perform logic
operations on data -- AND, OR, etc.
– Arithmetic: addition, subtraction, increment,
etc.
– Flow control: instructions that change the
sequence of execution of a program -conditional and unconditional branches, stack
operations, etc.
– Input / Output operations
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EE 4535 – Packet 3
The instruction set specifies the kinds of
data transfers and transformations that can
occur in the machine
Instructions can be grouped into 5 broad
categories
9
An instruction generally consists of an
opcode and some operand(s)
HC11 instructions are of different lengths
(1 to 5 bytes)
EE 4535 – Packet 3
10
5
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The instruction set is summarized in Table
A.1 of the text, Appendix A of the HC11
Reference Manual, and M68HC11 E Series
Programming Reference Guide
– In general, an n-bit opcode is capable of
specifying any one of 2n instructions
– With 8-bit opcodes, 256 distinct instructions are
possible
– 68HC11 has more than 300 actual instructions
» 145 "basic" instructions plus “addressing
variations”
» 1 or 2 bytes of storage specify the opcode!
– Lists instruction mnemonic, brief description of
the operation, addressing modes available,
machine code format of the instruction, timing
information, and effect on condition code
registers
EE 4535 – Packet 3
Opcode construction
11
EE 4535 – Packet 3
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6
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1-byte opcodes
– Most opcodes use just 1 byte
– Downward compatible with 6801
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– An instruction is made up of an opcode and a
set of operands
» Opcode may be one or two bytes
» Instructions may use 0, 1, 2, or 3 operands
� Operands may be 1 or 2 bytes
– Instruction lengths range from 1 to 5 bytes
2-byte opcodes
– Most 2-byte instructions deal with register Y,
which was not present in the 6801 processor
– It takes longer to fetch and execute 2-byte
opcodes
– New instructions use a "pre-byte", which
signals that another opcode byte follows:
» $18, $1A, or $CD
� Ex.
INX
$08
INY
$18 $08
EE 4535 – Packet 3
Instruction format
Example (assume this is stored at address $E000):
LDAA #$FF
; load ACCA with the
; value $FF
Machine code:
$E000
$86
$E001
$FF
13
EE 4535 – Packet 3
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7
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Fetch/Execute operation:
– LDAA #$FF
– First clock cycle
Fetch/Execute operation
– LDAA #$FF
– Second clock cycle
CPU
Control sequencer
Instruction Decoder
ALU
CPU
Control sequencer
Instruction Decoder
ALU
86
ACCA
ACCA
FF
PC
E000
PC
E001
AR
E000
AR
E001
Addr Bus
E000
EE 4535 – Packet 3
Memory
E000
E001
E002
FF
Addr Bus
86
FF
FE
86
E001
Data Bus
15
EE 4535 – Packet 3
Memory
E000
E001
E002
86
FF
FE
FF
Data Bus
16
8
Addressing modes
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How does the instruction specify the
location of data?
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The HC11 supports 5 different
addressing modes
– Immediate addressing
» One operand is included as part of the
instruction word
» Other operand (if needed) comes from an
implied register
» Instruction length: 2 - 4 bytes
» Specified operand is a constant and cannot
be altered at run time
» Mode is denoted by a # before the operand
value
» Example:
– Inherent Addressing
» Operands are specified implicitly in the
opcode itself
» Operands are contained in the registers
instead of memory
» Instruction length: 1 or 2 bytes
» Examples:
� Register increment, clears
CLRA
� Register shift operations
ASLA
� Register additions
ABA
EE 4535 – Packet 3
LDAA
#$05
$86 $05
17
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9
– Direct addressing
» The operand included in the instruction
word is a memory address, specifying where
the data is located
» Second operand is an implied register
» Instruction length: 2 - 4 bytes
» Since an address is specified, the data value
itself can be changed during program
execution
� Address is a constant
» Address included in the instruction word is
only 1 byte
� Direct addressing can only be used to
reference locations $0000 -- $00FF -256 locations
» Example:
LDAA
– Extended addressing
» Same as direct addressing, but with 2 bytes
of address -- the full range of addresses can
be specified ($0000 to $FFFF)
» Instruction length: 3 or 4 bytes
» Example:
LDAA $0005
$B6 $00 $05
» Why have both modes?
$05
$96 $05
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EE 4535 – Packet 3
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10
Basic tour of the instruction set
– Indexed addressing
» The effective address of the data in memory is
computed as the sum of the value contained in an
index register (X or Y) and an offset (contained
in the instruction word)
» The offset is a 1-byte unsigned quantity
» Useful for table and array access
� Eg. LDAA
$56,X
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Load Instructions
– Transfer data from memory to register
– LDAA, LDAB, LDD, LDX, LDY, LDS
– Different addressing modes supported
» Assume the following memory contents:
0050
2000
40 41 42 43 44 45 46 47 - 48 49 4a 4b 4c 4d 4e 4f
50 51 52 53 54 55 56 57 - 58 59 5a 5b 5c 5d 5e 5f
$A6 $56
LDAA
LDAB
LDAA
LDD
– Relative addressing
» Similar to indexed addressing
-- uses PC value instead of the value in X or Y
» Instruction's offset value is added to the value in
the program counter to give the address of the
next instruction
» Used to specify branch addresses resulting from
jump commands
» Offset is an 8-bit 2's complement number
--ranges from -128 to +127 decimal
EE 4535 – Packet 3
#$56
$56
$2000
$2002
LDX
#$2000
LDAA $C, X
LDY
#$56
LDAB 0, Y
LDX
$5, X
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EE 4535 – Packet 3
; ACCA = $56 (immediate)
; ACCB = $46 (direct)
; ACCA = $50 (extended)
; ACCD = $5253 (extended)
; ACCA = $52, ACCB = $53
; IX = $2000 (immediate)
; ACCA = $5C (indexed)
; IY = $56 (immediate)
; ACCB = $46 (indexed)
; IX = ? (indexed)
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11
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Store Instructions
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Transfer Instructions
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Decrement Instructions
DEC opr
DECA
DECB
DEX
DEY
DES
– Transfer data from register to register
TAB
; ACCA � ACCB
TBA
; ACCB � ACCA
TAP
; ACCA � CCR
TPA
; CCR � ACCA
TXS
; IX � SP
TSX
; SP � IX
TYS
; IY � SP
TSY
; SP � IY
XGDX
; IX � ACCD
XDGY
; IY � ACCD
EE 4535 – Packet 3
Increment Instructions
INC opr
INCA
INCB
INX
INY
INS
– Transfer data from register to memory
– STAA, STAB, STD, STX, STY, STS
– Direct, extended, or indexed addressing
» No immediate addressing
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Clear Instructions
CLR opr
CLRA
CLRB
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EE 4535 – Packet 3
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12
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Rotate Instructions
– Shifts all 8 bits plus the Carry bit circularly one
position.
ROL
opr
ROLA
ROLB
ROR
opr
RORA
RORB
– Note: 9 rotates puts data back in original
position (not 8 as stated in text)
Rotate Instructions
– Example
» Assume C = 1, ACCA = $3B
1
0 0 1 1 1 0 1 1
C
b7
b0
» ROLA
1
0 0 1 1 1 0 1 1
C
b7
b0
» Result: C = 0, ACCA = $77
C
EE 4535 – Packet 3
b7
b0
25
EE 4535 – Packet 3
0
0 1 1 1 0 1 1 1
C
b7
b0
26
13
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Shift Instructions
Shift Instructions
– Arithmetic Shifts
» ASL opr, ASLA, ASLB, ASLD, ASR opr,
ASRA, ASRB, ASRD
– Logical Shifts
» LSL opr, LSLA , LSLB, LSLD, LSR opr,
LSRA, LSRB, LSRD
0
C
0
C
b7
EE 4535 – Packet 3
b0
b0
b7
b0
C
» ASR preserves sign bit
» ASL/ASR can be used to multiply/divide by 2
» What is the difference between ASL and LSL?
0
b7
b7
b0
C
27
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14
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Logical Instructions
– Bit-wise AND
ANDA opr
ANDB opr
– Add instructions
ABA
; ACCA + ACCB �
ACCA
ADDA opr
; ACCA + M � ACCA
ADDB opr
; ACCB + M � ACCB
ADDD opr
; ACCD + M � ACCD
ADCA opr
; ACCA+ M+ C � ACCA
ADCB opr
; ACCB+ M+ C � ACCB
ABX
; IX + ACCB � IX
ABY
; IY + ACCB � IY
– Subtract Instructions
SBA
; ACCA - ACCB � ACCA
SUBA opr
; ACCA - M � ACCA
SUBB opr
; ACCB - M � ACCB
SUBD opr
; ACCD - M � ACCD
SBCA opr
; ACCA - M - C � ACCA
SBCB opr
; ACCB - M - C � ACCB
– Bit-wise OR
ORA opr
ORB opr
– Bit-wise Exclusive-OR
EORA opr
EORB opr
– 1’s Complement
COM opr
COMA
COMB
EE 4535 – Packet 3
Arithmetic Instructions
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EE 4535 – Packet 3
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15
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Arithmetic Instructions
– Unsigned arithmetic
» Numbers range from $00 to $FF (0 to 255)
» The carry bit (C) is set if result is outside
range
– The same instructions are used for both signed
and unsigned arithmetic
» The CPU does not care whether the values
are signed or unsigned
� The arithmetic result is the same for both
cases
� C, V, and N bits are set based on
Boolean combinations of the operands
» Programmer must keep track of whether
values are signed or unsigned
� Whether to use the C or V bit to check
for overflow
– Signed arithmetic
» Numbers range from $80 to $7f (-128 to
+127)
» The overflow bit (V) is set if result is
outside range
» The negative bit (N) is set if result is
negative (same as MSB of result)
EE 4535 – Packet 3
Arithmetic instructions
31
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16
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Arithmetic Instructions
– Example:
» Add $56 + $B0
�
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Unsigned: $56 + $B0 = $106
Signed: $56 + $B0 = $06
LDAA #$56
LDAB #$B0
ABA
– MUL instruction
» Multiplies 8-bit unsigned values in ACCA
and ACCB, then puts the 16-bit result in
ACCD
� Note that this overwrites ACCA and
ACCB!
– If you’re multiplying by a power of 2, you may
want to use ASL instructions instead
» Why?
(86 + 176 = 262)
(86 + (-80) = 6)
;ACCA = $06, C = 1, V = 0
– Example:
» Add $56 to $60
�
�
Unsigned: $56 + $60 = $B6
Signed: $56 + $60 = $B6
LDAA #$56
LDAB #$60
ABA
EE 4535 – Packet 3
Multiplication
(86 + 96 = 182)
(86 + 96 = -74!!!)
;ACCA = $B6, C = 0, V = 1
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EE 4535 – Packet 3
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17
�
�
Binary Fractions
– Example:
» Multiply $20 x $35 (32 x 53 in decimal)
– Multiplying two 8-bit numbers gives 16-bit
result. What if you only want 8 bits?
– Different ways to interpret 8-bit numbers
» Unsigned integers
0 - 255
» Signed integers
-128 - +127
» Binary fractions
0-1
� $00 = 0/256 = 0
� $80 = 128/256 = 0.5
� $FF = 255/256 = 0.9961
– You can use the ADCA instruction after a MUL
to convert 16-bit result to 8-bit binary fraction
» MUL sets C to 1 if bit 7 of ACCB is 1
EE 4535 – Packet 3
Binary Fractions
» Unsigned integers:
$20 x $35 = 32 x 53 = 1696 = $6A0
LDAA #$20
LDAB #$35
MUL
; ACCD = $06A0, C = 1
; ACCA=$06, ACCB=$A0
» Binary fractions:
� (32 / 256) x (53 / 256) = 1696 / 65,536
= 6.625 / 256
≈ 7 / 256
LDAA #$20
LDAB #$35
MUL
; ACCD = $06A0, C = 1
ADCA #$00 ; now ACCA = $07
�
35
EE 4535 – Packet 3
36
18
�
Integer Division
�
– IDIV
» Divides 16-bit unsigned integer in ACCD by
16-bit unsigned integer in IX
» Puts quotient in IX, remainder in ACCD
– Example: 6 / 4
LDD
#$6
; ACCD = $6
LDX
#$4
; IX = $4
IDIV
; IX = $1, ACCD = $2
– FDIV
» Divides 16-bit binary fraction in ACCD by
16-bit fraction in IX
� 16-bit values between 0 and 1
» Puts quotient in IX, remainder in ACCD
» Often used to convert remainder from IDIV
into a fraction
» Example: 6/4
– Note: IDIV takes 41 cycles to execute
» You can use ASR instructions to divide by
powers of 2
� Only gives you the quotient, not the
remainder
– Divide by zero
» IX set to $FFFF, C set to 1
EE 4535 – Packet 3
Fractional Division
LDD #$6
LDX #$4
IDIV
; IX = $1, ACCD = $2
STX Somewhere
; store quotient
LDX #$4
; reload denominator
FDIV
; IX = $8000, ACCD = $0
; (Note $8000 = 0.5)
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EE 4535 – Packet 3
38
19
�
�
Floating point numbers
CCR Operations
CLC
; clear the C bit
CLV
; clear the V bit
SEC
; set the C bit
SEV
; set the V bit
– Can use SEC and CLC to set up the C bit prior
to rotate instructions, for example
– Used to increase the range of number
representation past that of integer formats
– Due to 8-bit CPU, IEEE floating point standard
is not supported on the HC11
– Motorola has a non-standard format
– Floating point routines can be downloaded from
the Motorola web site if you need these for
projects (you will not need them for the labs)
�
“No Operation” Instruction
NOP
– Does nothing but increment the PC
– Why would you need this?
EE 4535 – Packet 3
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EE 4535 – Packet 3
40
20
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Compare Instructions
�
– Compares two registers, or a register and a
memory location/immediate value
» Subtracts the two values
– Sets N, Z, V, C condition codes
– Does not change operands
– Example: Assume the 16-bit value $5100 is
stored at memory location $2000:
LDAA
LDAB
CBA
CBA
; ACCA - ACCB
CMPA opr
; ACCA - M
CMPB opr
; ACCB - M
CPD opr
; ACCD - M
CPX opr
; IX - M
CPY opr
; IY - M
– Can be used to check if two values are equal,
greater than/less than, etc.
» Often used before conditional branch
instruction
EE 4535 – Packet 3
Compare Instructions
CPD
41
EE 4535 – Packet 3
#$50
#$4F
; ACCA-ACCB = 1, so this
; sets N=0, Z=0, V=0, C=0
$2000 ; ACCD-M = $FF4F, so this
; sets N=1, Z=0, V=0, C=1
42
21
�
�
Test Instructions
– Like compare, but always compares register or
memory location with #$00
TST
TSTA
TSTB
Bit Set/Clear Instructions
– Used to set or clear multiple bits in a memory
location
opr
BSET opr mask
BCLR opr mask
– 1’s in mask specify which bits are set or
cleared. Other bits are unaffected.
– Example: Assume IX = $20, memory location
$34 contains the value $1A
– Why not use CMP instructions?
BSET $14,X $31 ; now location $34 = $3B
BCLR $34 $1C ; now location $34 = $23
EE 4535 – Packet 3
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EE 4535 – Packet 3
44
22
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Bit Test Instructions
�
– Performs logical AND and modifies condition
codes N and Z (V is always cleared, C is
unaffected)
– Does not modify the operands
Flow control with looping and branching
– Flow control is the process of
» Making decisions
» Performing operations in sequence
» Repeating identical operations
BITA opr
BITB opr
– Example: Assume location $2000 contains the
value $1A
LDAA
LDAB
BITA
BITB
#$3F
#$05
#$03
$2000
; N=0, Z=0
; N=0, Z=1
Fig 2.21 Flow control mechanisms
EE 4535 – Packet 3
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EE 4535 – Packet 3
46
23
�
Unconditional branching
�
– The 68HC11 uses the command JMP to
perform unconditional (absolute) branches
JMP opr
» Target address can be anywhere within
processor's 64K range
» To perform the jump, the target address is
simply loaded into the program counter
register
» Instruction uses extended or indexed
addressing modes
� Extended mode instruction is 3 bytes
long -- the opcode, and 2 bytes that
specify the jump address (high byte then
low byte)
– Normally, you would use a label to
specify the address
� Indexed mode is 2 bytes long -- opcode
plus relative offset (note offset is
unsigned value)
EE 4535 – Packet 3
Unconditional branching
– You can also use BRA (Branch Always)
instruction
BRA
rel
– Uses relative addressing
» rel is 8-bit two’s-complement number
» Added to the PC
» Limited range
– There is also a Branch Never instruction
BRN
rel
– When would you use this?
47
EE 4535 – Packet 3
48
24
�
�
Relative addressing
– Offset is added to the PC to cause the branch
– 8-bit offset
» Range is -128 to +127
– Destination address is actually relative to the
address following the branch instruction
» Why?
– Calculating destination addresses:
– The assembler usually handles the calculation
of relative addresses
» In your program, put a label on the
destination instruction, and then the branch
instruction can reference the label
» Example:
ORG $B600
Label: LDAA $100
; get current val
INCA
; increment it
STAA $100
; store updated val
BRA Label ; repeat
PCnew = PCold + T + rel
»
»
»
»
EE 4535 – Packet 3
Relative addressing
PCold is address of branch instruction
PCnew is destination address
rel is the relative address
T is 2 for most instructions
� T = 4 for BRCLR, BRSET with indexed
addressing using IX
� T = 5 for BRCLR, BRSET with indexed
addressing using IY
Object code:
B600
B603
B604
B607
49
EE 4535 – Packet 3
B6 01 00
4C
B7 01 00
20 F7
50
25
�
�
Conditional branching
– Here, the branch instruction checks if a
(specified) condition is true or false
» Uses condition codes in CCR
� Use branch instruction after setting the
condition codes
» If it is true, branch to target address
» If false -- no branch, continue execution at
the next instruction
– Uses only relative addressing to specify the
target address
» Limited to 8-bit relative offset
» Textbook shows a way to combine a
conditional branch with a JMP to overcome
this limit
EE 4535 – Packet 3
Conditional Branching
– Simple conditional branches
BCS rel
; branch if C=1
BCC rel
; branch if C=0
BMI rel
; branch if N=1
BPL rel
; branch if N=0
BVS rel
; branch if V=1
BVC rel
; branch if V=0
BEQ rel
; branch if Z=1
BNE rel
; branch if Z=0
51
EE 4535 – Packet 3
52
26
�
�
Conditional Branching
– Signed branches
» Use when working with signed values
» Branches are based on N, Z, and V bits only
BGT
BLT
BGE
BLE
BEQ
BNE
EE 4535 – Packet 3
rel
rel
rel
rel
rel
rel
Conditional Branching
– Unsigned branches
» Use when working with unsigned values
» Branches based on C and Z condition codes
» Note that Motorola uses the terms “greater
than” and “less than” to refer to signed
values, and “higher” and “lower” to refer to
unsigned values
; greater than
; less than
; greater than or equal
; less than or equal
; equal
; not equal
BHI
BHS
BLO
BLS
BEQ
BNE
53
EE 4535 – Packet 3
rel
rel
rel
rel
rel
rel
; higher
; higher or same (same as BCC)
; lower (same as BCS)
; lower or same
; equal
; not equal
54
27
» Conditional branching can also be based on
bit values in a particular memory value
� Format:
�
Fetch/Execute Operation
– BNE LOOP
– First clock cycle
BRCLR opr mask rel
BRSET opr mask rel
CPU
Control sequencer
Instruction Decoder
ALU
– opr is the memory address (direct or
indexed addressing is used)
– mask identifies the bits to check (set
to 1, others are 0) in an AND format
– rel is the relative branch address
� Example:
BRSET $10 $05 new
Branch to address "new" if bits 0 and 2
of the value stored at location $10 are
both 1
ACCA
PC
E010
AR
E010
Addr Bus
E010
EE 4535 – Packet 3
26
55
EE 4535 – Packet 3
Memory
E010
E011
E012
26
F6
B7
26
Data Bus
56
28
�
�
Fetch/Execute Operation
– BNE LOOP
– Second clock cycle
Fetch/Execute Operation
– BNE LOOP
– Third clock cycle
– New PC = $E012 + $FFF6 = $E008
CPU
Control sequencer
Instruction Decoder
ALU
CPU
Control sequencer
Instruction Decoder
ALU
ACCA
PC
E011
AR
E011
ACCA
PC
E012
AR
Addr Bus
E011
EE 4535 – Packet 3
Memory
E010
E011
E012
Addr Bus
26
F6
B7
F6
Data Bus
FFFF
57
EE 4535 – Packet 3
Memory
E010
E011
E012
26
F6
B7
Data Bus
58
29
Halting program execution
– How do we stop a program once its
execution is finished?
– What happens at the "end" of our
program?
» BRA $ or BRA *
� Used in our text's examples
� Infinite loop branching back on itself
� $ (or *) denotes "current" address
(location of BRA instruction)
� Program never really terminates, so use
with caution
» SWI
� This instruction causes a software
generated interrupt to occur
� Upon occurrence, can jump to a location
in memory and execute what's found
there
� Some systems use this approach to return
to a monitor routine after program
execution is finished
– STOP
» This instruction stops the execution
by disabling all system clocks and
putting the system in a minimumpower standby mode
» Only ways to recover from a STOP
are:
� Perform a system RESET*
� Generate a valid system interrupt
» Avoid using this -- catastrophic
EE 4535 – Packet 3
59
EE 4535 – Packet 3
60
30