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RX Voltage Detection Circuit (LVD) and
Power-On Reset (POR)
Renesas Electronics America Inc.
Ver. 1.00
© 2011 Renesas Electronics America Inc. All rights reserved.
Course Introduction
 Purpose
 Learn RX reset sources & voltage detection
 Content
 Voltage Detection Circuit (LVD)
 LVD Control & Status Registers
 RX Reset Sources
 Determining Reset Source
 Learning Time
 20 Minutes
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© 2011 Renesas Electronics America Inc. All rights reserved.
RX Voltage Detection Circuit (LVD)
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Monitors Vcc voltage level
Interrupt and/or reset at two fixed voltages: Vdet1 & Vdet2
Off at power up by default
Key code register protects against unwanted modification
Vcc
Vdet2
Vdet1
VPOR
Reset
3
© 2011 Renesas Electronics America Inc. All rights reserved.
LVD Key Code Register
 LVD Key Code Register (LVDKEYR)
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Enables writing to LVD Control Register (LVDCR)
Write 0x3C to enable writing
Other values lock out changes
Locked on reset
LVD Key Code Register (LVDKEYR)
After reset
4
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
© 2011 Renesas Electronics America Inc. All rights reserved.
Low-Voltage Detection Control Register
 LVD Control Register (LVDCR)
 LVD1E, LVD2E
– Enable bits for LVD1 and LVD2 (1 = enabled)
 LVD1RI, LV2RI
– Selects interrupt or reset generation for each
– 0=Reset, 1=Interrupt
 Interrupts are NMI’s (set NMIER.LVDEN in the ICU)
 LVD1 and LVD2 are locked & disabled after reset
 Lock it after changes with LVDKEYR!
LVD Control Register (LVDCR)
After reset
5
b7
b6
b5
b4
b3
b2
b1
b0
LVD2E
LVD2RI
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LVD1E
LVD1RI
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0
0
0
0
0
0
0
0
© 2011 Renesas Electronics America Inc. All rights reserved.
Reset Status Register
 Reset Status Register (RSTR)
 LVD1F, LVD2F
– Indicate state of LVD1 and LVD2 (1=detected)
 PORF
– 0=Reset caused by something other than POR
– 1=POR was detected
 DPSRSTF
– Indicates reason for exit from deep software stby mode
Reset Status Register (RSTR)
After reset
6
b7
b6
b5
b4
b3
b2
b1
b0
DPSRSTF
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LVD2F
LVD1F
PORF
0
0
0
0
0
0
0
0
© 2011 Renesas Electronics America Inc. All rights reserved.
RX Resets
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7
Power-on reset
Pin reset
Voltage-monitoring
Deep software standby reset
Independent watchdog timer
Watchdog timer
© 2011 Renesas Electronics America Inc. All rights reserved.
Power-on reset
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8
Generated internally
RES# pin high when power is applied
VCC rises above VPOR (2.58V typ.)
Power-on reset time (tPOR) of 20-50ms (35 ms typ.)
RSTSR.PORF = 1
Don’t place capacitor on RES# line!
© 2011 Renesas Electronics America Inc. All rights reserved.
Pin Reset
 Drive RES# low
 tRESW: Hold RES# low for the longer of:
 20 tcyc
 1.5 uS
 All reset-related status registers are cleared
9
© 2011 Renesas Electronics America Inc. All rights reserved.
Voltage-Monitoring Reset
Internally generated by LVD
Caused by VCC < Vdet1 or VCC < Vdet2
Internal reset starts tdet (max 200uS) after VCC falls
Rising edge on VCC tVOFF (min 200uS) after falling edge
Power-on reset time (tPOR) of 20-50ms (35 typ.) starts after
rising edge
 RSTSR.LVDnF = 1 (n=1 or 2)
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© 2011 Renesas Electronics America Inc. All rights reserved.
Deep Software Standby Reset
 Generated when deep software stdby exited by interrupt
 Startup delay specified in DPSWCR.WTSTS[5:0]
 RSTSR.DPSRSTF = 1
11
© 2011 Renesas Electronics America Inc. All rights reserved.
Watchdog Resets
 Independent Watchdog (IWDT)
 Clock source = OCOCLK
 IWDTSR.UNDFF indicates timeout/reset
 Watchdog Timer (WDT)
 Clock source = PCLK / divisor
 RSTCSR.WOVF indicates timeout/reset
 Also drives WDT# pin (do NOT connect to RST# pin!)
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© 2011 Renesas Electronics America Inc. All rights reserved.
Determining Reset Source
13
© 2011 Renesas Electronics America Inc. All rights reserved.
Summary
 RX Voltage Detection Circuit (LVD)
 LVD Control & Status Registers
 RX Power-On Reset (POR)
 Other RX Reset Sources
 Determining Reset Source
 Thank you!
14
© 2011 Renesas Electronics America Inc. All rights reserved.
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Thank You
Renesas Electronics America Inc.
© 2011 Renesas Electronics America Inc. All rights reserved.