Download Lecture 17 - Harvey Mudd College

Introduction to
CMOS VLSI
Design
Lecture 17:
SRAM
David Harris
Harvey Mudd College
Spring 2007
Outline
 Memory Arrays
 SRAM Architecture
– SRAM Cell
– Decoders
– Column Circuitry
– Multiple Ports
 Serial Access Memories
17: SRAM
CMOS VLSI Design
Slide 2
Memory Arrays
Memory Arrays
Random Access Memory
Read/Write Memory
(RAM)
(Volatile)
Static RAM
(SRAM)
Dynamic RAM
(DRAM)
Mask ROM
Programmable
ROM
(PROM)
17: SRAM
Content Addressable Memory
(CAM)
Serial Access Memory
Read Only Memory
(ROM)
(Nonvolatile)
Shift Registers
Serial In
Parallel Out
(SIPO)
Erasable
Programmable
ROM
(EPROM)
Parallel In
Serial Out
(PISO)
Electrically
Erasable
Programmable
ROM
(EEPROM)
CMOS VLSI Design
Queues
First In
First Out
(FIFO)
Last In
First Out
(LIFO)
Flash ROM
Slide 3
Array Architecture
 2n words of 2m bits each
 If n >> m, fold by 2k into fewer rows of more columns
wordlines
bitline conditioning
bitlines
row decoder
memory cells:
2n-k rows x
2m+k columns
n-k
column
circuitry
k
n
column
decoder
2m bits
 Good regularity – easy to design
 Very high density if good cells are used
17: SRAM
CMOS VLSI Design
Slide 4
12T SRAM Cell
 Basic building block: SRAM Cell
– Holds one bit of information, like a latch
– Must be read and written
 12-transistor (12T) SRAM cell
– Use a simple latch connected to bitline
– 46 x 75 l unit cell
bit
write
write_b
read
read_b
17: SRAM
CMOS VLSI Design
Slide 5
6T SRAM Cell
 Cell size accounts for most of array size
– Reduce cell size at expense of complexity
 6T SRAM Cell
– Used in most commercial chips
– Data stored in cross-coupled inverters
 Read:
bit
– Precharge bit, bit_b
word
– Raise wordline
 Write:
– Drive data onto bit, bit_b
– Raise wordline
17: SRAM
CMOS VLSI Design
bit_b
Slide 6
SRAM Read




Precharge both bitlines high
Then turn on wordline
One of the two bitlines will be pulled down by the cell
Ex: A = 0, A_b = 1
– bit discharges, bit_b stays high
– But A bumps up slightly
 Read stability
– A must not flip
bit_b
bit
word
P1 P2
N2
N4
A
A_b
N1 N3
A_b
bit_b
1.5
1.0
bit
word
0.5
A
0.0
0
100
200
300
400
500
600
time (ps)
17: SRAM
CMOS VLSI Design
Slide 7
SRAM Read




Precharge both bitlines high
Then turn on wordline
One of the two bitlines will be pulled down by the cell
Ex: A = 0, A_b = 1
– bit discharges, bit_b stays high
– But A bumps up slightly
 Read stability
– A must not flip
– N1 >> N2
bit_b
bit
word
P1 P2
N2
N4
A
A_b
N1 N3
A_b
bit_b
1.5
1.0
bit
word
0.5
A
0.0
0
100
200
300
400
500
600
time (ps)
17: SRAM
CMOS VLSI Design
Slide 8
SRAM Write




Drive one bitline high, the other low
Then turn on wordline
Bitlines overpower cell with new value
Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
– Force A_b low, then A rises high
 Writability
– Must overpower feedback inverter
bit_b
bit
word
P1 P2
N2
A
N4
A_b
N1 N3
A_b
A
1.5
bit_b
1.0
0.5
word
0.0
0
100
200
300
400
500
600
700
time (ps)
17: SRAM
CMOS VLSI Design
Slide 9
SRAM Write




Drive one bitline high, the other low
Then turn on wordline
Bitlines overpower cell with new value
Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
– Force A_b low, then A rises high
 Writability
– Must overpower feedback inverter
– N2 >> P1
bit_b
bit
word
P1 P2
N2
A
N4
A_b
N1 N3
A_b
A
1.5
bit_b
1.0
0.5
word
0.0
0
100
200
300
400
500
600
700
time (ps)
17: SRAM
CMOS VLSI Design
Slide 10
SRAM Sizing
 High bitlines must not overpower inverters during
reads
 But low bitlines must write new value into cell
bit_b
bit
word
weak
med
med
A
A_b
strong
17: SRAM
CMOS VLSI Design
Slide 11
SRAM Column Example
Read
Write
Bitline Conditioning
Bitline Conditioning
2
2
More
Cells
More
Cells
word_q1
word_q1
SRAM Cell
bit_b_v1f
out_b_v1r
H
bit_v1f
H
bit_b_v1f
bit_v1f
SRAM Cell
write_q1
out_v1r
data_s1
1
2
word_q1
bit_v1f
out_v1r
17: SRAM
CMOS VLSI Design
Slide 12
SRAM Layout
 Cell size is critical: 26 x 45 l (even smaller in industry)
 Tile cells sharing VDD, GND, bitline contacts
GND
BIT BIT_B GND
VDD
WORD
Cell boundary
17: SRAM
CMOS VLSI Design
Slide 13
Decoders
 n:2n decoder consists of 2n n-input AND gates
– One needed for each row of memory
– Build AND from NAND or NOR gates
Static CMOS
A1
Pseudo-nMOS
A0
A1
word0
word1
17: SRAM
1
1
8
A1
1
4
A0
1
A0
word0
word
word1
word2
word2
word3
word3
CMOS VLSI Design
A0
1/2
4
16
A1
1
1
2
8
word
Slide 14
Decoder Layout
 Decoders must be pitch-matched to SRAM cell
– Requires very skinny gates
A3
A3
A2
A2
A1
A1
A0
A0
VDD
word
GND
buffer inverter
NAND gate
17: SRAM
CMOS VLSI Design
Slide 15
Large Decoders
 For n > 4, NAND gates become slow
– Break large gates into multiple smaller gates
A3
A2
A1
A0
word0
word1
word2
word3
word15
17: SRAM
CMOS VLSI Design
Slide 16
Predecoding
 Many of these gates are redundant
– Factor out common
gates into predecoder
– Saves area
– Same path effort
A3
A2
A1
A0
predecoders
1 of 4 hot
predecoded lines
word0
word1
word2
word3
word15
17: SRAM
CMOS VLSI Design
Slide 17
Column Circuitry
 Some circuitry is required for each column
– Bitline conditioning
– Sense amplifiers
– Column multiplexing
17: SRAM
CMOS VLSI Design
Slide 18
Bitline Conditioning
 Precharge bitlines high before reads

bit
bit_b
 Equalize bitlines to minimize voltage difference
when using sense amplifiers

bit
17: SRAM
bit_b
CMOS VLSI Design
Slide 19
Sense Amplifiers
 Bitlines have many cells attached
– Ex: 32-kbit SRAM has 128 rows x 256 cols
– 128 cells on each bitline
 tpd  (C/I) DV
– Even with shared diffusion contacts, 64C of
diffusion capacitance (big C)
– Discharged slowly through small transistors
(small I)
 Sense amplifiers are triggered on small voltage
swing (reduce DV)
17: SRAM
CMOS VLSI Design
Slide 20
Differential Pair Amp
 Differential pair requires no clock
 But always dissipates static power
sense_b
bit
P1
P2
N1
N2
sense
bit_b
N3
17: SRAM
CMOS VLSI Design
Slide 21
Clocked Sense Amp
 Clocked sense amp saves power
 Requires sense_clk after enough bitline swing
 Isolation transistors cut off large bitline capacitance
bit
bit_b
isolation
transistors
sense_clk
regenerative
feedback
sense
17: SRAM
sense_b
CMOS VLSI Design
Slide 22
Twisted Bitlines
 Sense amplifiers also amplify noise
– Coupling noise is severe in modern processes
– Try to couple equally onto bit and bit_b
– Done by twisting bitlines
b0 b0_b b1 b1_b b2 b2_b b3 b3_b
17: SRAM
CMOS VLSI Design
Slide 23
Column Multiplexing
 Recall that array may be folded for good aspect ratio
 Ex: 2 kword x 16 folded into 256 rows x 128 columns
– Must select 16 output bits from the 128 columns
– Requires 16 8:1 column multiplexers
17: SRAM
CMOS VLSI Design
Slide 24
Tree Decoder Mux
 Column mux can use pass transistors
– Use nMOS only, precharge outputs
 One design is to use k series transistors for 2k:1 mux
– No external decoder logic needed
B0 B1
B2 B3
B4 B5
B6 B7
B0 B1
B2 B3
B4 B5
B6 B7
A0
A0
A1
A1
A2
A2
Y
17: SRAM
to sense amps and write circuits
CMOS VLSI Design
Y
Slide 25
Single Pass-Gate Mux
 Or eliminate series transistors with separate decoder
A1
A0
B0 B1
B2 B3
Y
17: SRAM
CMOS VLSI Design
Slide 26
Ex: 2-way Muxed SRAM
2
More
Cells
More
Cells
word_q1
A0
A0
write0_q1
2
write1_q1
data_v1
17: SRAM
CMOS VLSI Design
Slide 27
Multiple Ports
 We have considered single-ported SRAM
– One read or one write on each cycle
 Multiported SRAM are needed for register files
 Examples:
– Multicycle MIPS must read two sources or write a
result on some cycles
– Pipelined MIPS must read two sources and write
a third result each cycle
– Superscalar MIPS must read and write many
sources and results each cycle
17: SRAM
CMOS VLSI Design
Slide 28
Dual-Ported SRAM
 Simple dual-ported SRAM
– Two independent single-ended reads
– Or one differential write
bit
bit_b
wordA
wordB
 Do two reads and one write by time multiplexing
– Read during ph1, write during ph2
17: SRAM
CMOS VLSI Design
Slide 29
Multi-Ported SRAM
 Adding more access transistors hurts read stability
 Multiported SRAM isolates reads from state node
 Single-ended design minimizes number of bitlines
bA bB bC
bD bE bF bG
wordA
wordB
wordC
wordD
wordE
wordF
wordG
write
circuits
read
circuits
17: SRAM
CMOS VLSI Design
Slide 30
Serial Access Memories
 Serial access memories do not use an address
– Shift Registers
– Tapped Delay Lines
– Serial In Parallel Out (SIPO)
– Parallel In Serial Out (PISO)
– Queues (FIFO, LIFO)
17: SRAM
CMOS VLSI Design
Slide 31
Shift Register
 Shift registers store and delay data
 Simple design: cascade of registers
– Watch your hold times!
clk
Din
Dout
8
17: SRAM
CMOS VLSI Design
Slide 32
Denser Shift Registers
 Flip-flops aren’t very area-efficient
 For large shift registers, keep data in SRAM instead
 Move read/write pointers to RAM rather than data
– Initialize read address to first entry, write to last
– Increment address on each cycle
Din
clk
11...11
reset
17: SRAM
counter
counter
00...00
readaddr
writeaddr
dual-ported
SRAM
Dout
CMOS VLSI Design
Slide 33
Tapped Delay Line
 A tapped delay line is a shift register with a
programmable number of stages
 Set number of stages with delay controls to mux
– Ex: 0 – 63 stages of delay
clk
delay2
CMOS VLSI Design
SR1
delay3
SR2
17: SRAM
delay4
SR4
delay5
SR8
SR16
SR32
Din
delay1
Dout
delay0
Slide 34
Serial In Parallel Out
 1-bit shift register reads in serial data
– After N steps, presents N-bit parallel output
clk
Sin
P0
17: SRAM
P1
P2
CMOS VLSI Design
P3
Slide 35
Parallel In Serial Out
 Load all N bits in parallel when shift = 0
– Then shift one bit out per cycle
P0
P1
P2
P3
shift/load
clk
Sout
17: SRAM
CMOS VLSI Design
Slide 36
Queues
 Queues allow data to be read and written at different
rates.
 Read and write each use their own clock, data
 Queue indicates whether it is full or empty
 Build with SRAM and read/write counters (pointers)
WriteClk
WriteData
FULL
17: SRAM
ReadClk
Queue
ReadData
EMPTY
CMOS VLSI Design
Slide 37
FIFO, LIFO Queues
 First In First Out (FIFO)
– Initialize read and write pointers to first element
– Queue is EMPTY
– On write, increment write pointer
– If write almost catches read, Queue is FULL
– On read, increment read pointer
 Last In First Out (LIFO)
– Also called a stack
– Use a single stack pointer for read and write
17: SRAM
CMOS VLSI Design
Slide 38