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0806EF4-Agilent.doc
Keywords: optimization, parameters, testing
Editorial Feature Tab: Method-Tools -- Parameter Swept Optimization
@head: Create A CMOS Design Using Swept Optimization
@deck: Parameter sweeping and optimization techniques help to meet requirements so that a
balanced trade-off can be performed.
@text: Parameter value tradeoffs are part of the everyday design process. Say, for instance, that a
plot with requirements versus parameter values was available so that a tradeoff among all of the
requirements could be made. It would lead to a much better design at first pass while resulting in
less design iterations. As a result, designs would reach the market faster. This article explains
how to use a swept-optimization technique using a high-level simulator to complete the design
without any manual calculations.
Any design methodology is best illustrated by an example. In this case, there is a high-quality
reference current source of 1 mA (Iref). The desired output current is 100 μA ±5%. Swept
optimization will be used to design a simple current mirror (SCM) as shown in Figure 1. The
SCM also is required to have a minimum output voltage of 1.5 V and a minimum output
resistance of 100 KΩ. There will be no bias voltage restrictions (in other words, assume that any
DC voltage required can be made available with some extra circuitry). There is a stipulation,
however, that no DC voltage shall exceed 5 V.
In a computer-aided-design (CAD) approach, various techniques can be used to find appropriate
transistor dimensions in order to meet the requirements for a CMOS design. The designer can try
parameter sweeps, using trial and error, or the tuning process that’s demonstrated next. During
tuning, one or more parameters, such as channel width, are varied. The simulated results are
updated automatically. The advantage is that the data charts can keep a history of the different
trials, which helps the designer decide whether to increase or decrease certain values in real time.
Once the desired output is obtained, the designer stops the tuning process. The simulator
automatically updates the affected values. Following a channel-width tuning session for M2, the
final device dimensions were selected (see Figure 2).
Note that the current accuracy requirement is met. The value of VGS=1.5 V was selected because
it is best to have a design with the smallest input DC voltage possible. The current values show
that there is better than ±4% current accuracy over the entire output voltage range. This indicates
that the SCM can satisfy the output current requirements. The value of the drain to source
resistance exceeds the requirement of 100 KΩ. The plot for rds indicates better than 159.9 KΩ at
the minimum voltage and increasing as the output voltage within the voltage range of interest
(1.5 ≤ VDS ≤ 3.5).
Shifting focus to the input side of the current mirror, note the diode-connected configuration.
From the previous output side analysis, VDS=VGS=1.5 V for the input MOSFET. Using the
manual tuning technique, the dimensions of this transistor can be determined.
Based on the techniques explained previously, the final design shown in Figure 1 was obtained.
The schematic has been annotated with the nominal DC solution. Note that the input current is
1.0 mA for VDS=1.5 V. For the nominal output voltage of 2.5 V, the output current is 101 µA.
To verify that the minimum output voltage requirements for current and resistance were met, the
same setup shown was used along with an output voltage sweep. The results are shown in Figure
2. The design has met the current requirements for the full output voltage range (within ±4%).
The resistance values also meet the initial requirements.
At this point, the question becomes whether any other existing combination of dimensions and
voltages improves this configuration’s performance. Notice that VGS=1.5 V is selected. It isn’t an
arbitrary voltage, however. It represents the available input voltage for the reference current
source. The designer would benefit in the design effort if a plot with several widths for the output
transistor were available. A tradeoff among the requirements could then be made. Such an
analysis is possible using a high-level simulator, such as ADS. The process involves sweeping
the value of the channel width of the output transistor (M2) and letting the simulator optimize the
width of the input transistor (M1). Output current specifications can then be met at a certain
output voltage (in this case, the middle of the output range--2.5 V--was chosen).
An optimization is a simulation that modifies a set of parameter values to satisfy certain design
goals. To have a successful optimization, the first step is to have a successful nominal
simulation. If that simulation fails to execute, the optimizer cannot complete the task. This is one
of the reasons that a tuning session was done. The user must set up the desired goals
(requirements) and specify the parameters that are to be varied during optimization (the
optimizable parameters). The user then selects an optimizer type. The software supports several
optimizer types. For this article, the gradient optimizer was chosen based on the author’s
experience working with CMOS circuits and their optimization.
If the error termination condition between the simulated response and the desired goal is met, the
optimization is deemed successful. After each of the iterations, the optimizer calculates the
amount of error. If it meets the requirements, the simulation stops and the user can update the
optimizable values. The optimizer also has a requirement for the maximum number of iterations
that it can perform before it stops. The optimizer continues to perturb the parameters and
simulate the circuit until it either meets the goals or reaches the maximum number of iterations
specified by the user.
In each successive iteration, the optimizable variable values are selected based entirely on the
gradient search. Here, a simple gradient search is used and there are no constraints. As a result,
one can find problems where the Gradient Optimizer fails. For example, the algorithm gets stuck
in a local minimum and cannot find the global minimum. In these cases, another algorithm must
be used. This problem was not encountered with the circuits analyzed for this article.
The results of a swept-optimization analysis of the SCM in Figure 1 are shown in Figure 3. The
reader may think that the charts point to width1=2.0 μm as a better option. After all, the current
is well within the limit throughout the entire voltage range as well as the output resistance.
However, the table at the top of Figure 3 provides a different view. The smaller width requires a
higher input voltage (VIN) and a higher input resistance (RIN), which are both desired to be as
small as possible. This type of possible tradeoff cannot be easily analyzed using manual
approximations.
The swept-optimization technique can be used for more complex circuits, such as a ring
oscillator and an LC oscillator (see Figure 4). For the ring oscillator, the results of sweeping the
width value of the nmos transistors and bias voltage are shown. The intent of the optimizer is to
keep all of the zero crossings for all of the stages close to zero. The signal will then be
symmetrical.
For the LC oscillator, swept optimization is actually used to gain further insight into the design.
In a real application, the VCO may end up in a phase-locked loop (PLL). That PLL will have
loop dynamics that will keep the frequency of oscillation constant. But what would happen to the
output VCO phase noise if a different bias current is used and the VDD bias voltage is changed?
The required tuning voltage range and the channel width of M3, which is required to implement
the bias current, also are of interest. The ability to look at all of these conflicting requirements
and the required value of the design parameter (in other words, the width of M3) is very valuable
information for the designer. This ability is made possible by using the swept-optimization
technique.
Swept-Optimization Implementation
The swept-optimization technique sweeps a parameter (for example, the width of M2 for the
SCM). It then uses optimization to determine other values so that the requirements are met (for
example, the width of M1 for the SCM). Next, the circuit is analyzed with the optimum values
that were just found. The swept value is then increased and the process is repeated (see Figure 5).
The swept-optimization setup for the SCM from Figure 1 is illustrated in Figure 5. However,
only the simulation controllers are shown here. The SCM setup can be used to explain how the
swept-optimization technique is implemented. The steps are:
1. Select a parameter that you want to increment (swept value) to see the impact that it has
on the circuit. The increment is a predefined fixed value that must be selected by the
designer. Sweep the value of the width of M2 for the SCM. For that, we chose an
increment of 0.5 μm. We also opted to start the sweep at a width of 2.0 μm and stop at
5.0 μm. This is the function of the top parameter sweep (“Sweep3”) of Figure 5.
2. If W2 is varied, W1 (width of M1) needs to be calculated so that the output current
specification is met. In the swept-optimization technique, the optimizer “figures out” the
value of W1 (optimum value). For this reason, Sweep3 specifies that the simulation for
each swept value is an optimization (Optim1). This step eliminates the need for any
manual calculations.
3. Instruct the simulator to run a series of analyses with the value that it "figures out.” Note
that the FinalAnalysis from the Optim1 controller calls out a parameter sweep (Sweep1)
in Figure 5.
4. The Sweep1 controller has no SweepVar specified. The field is blank so that it can be
used as a simulation sequencer. Run two simulations: DC1 and Sweep2.
5. The DC1 controller runs a DC simulation with a sweep of the output DC voltage. The
results from this simulation produce the current accuracy and input voltage data for the
characterization curves.
6. The Sweep2 parameter sweep is used for the AC data necessary for the output and input
resistance characterization data. Note how the output DC voltage is swept. For each
output DC voltage, an AC simulation (“AC1”) is run. That simulation is used to calculate
Rin and Rout.
Wilfredo Rivas-Torres obtained his BSEE from Universidad Politecnica de Puerto Rico (UPPR)
in May 1988. He received his MSEE from Florida Atlantic University in May 2004. He is
presently with Agilent Technologies Inc. as an Applications Engineer in the EEsof Technical
Support group. Prior to joining Agilent, Rivas-Torres worked as an RF engineer at various
companies. He has over 18 years of experience. Rivas-Torres can be reached at wilfredo_rivastorres@agilent.com or by calling (800) 473-3763.
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Captions:
Figure 1: Here is a simple-current-mirror (SCM) design and DC annotation.
Figure 2: The SCM design using tuning results is shown here.
Figure 3: The SCM swept-optimization results are depicted here.
Figure 4: Results are shown for a ring oscillator and an LC oscillator.
Figure 5: Here is the setup for the SCM swept-optimization controllers.