Download 2009 Ismael Firas - Techniques for Low Power ASIC Design

TECHNIQUES FOR
LOW-POWER-ASIC
DESIGN
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JTAG
Ismael Firas
INTRODUCTION

Low Power design is all about reducing one or
several parts of the power equation.
Dynamic power.
 Leakage/Static power.
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
In the past:


Over all power density has essentially stayed the
same for every process reduction.
ITRS Prediction in 2005:
at 65-nm node dynamic power density and leakage
power density would increase by 1.43 and 2.5,
respectively.
 at 45-nm node we will get 2 and 6.5 respectively.


In realty :
at 65-nm designs, processes lose as much as half
their power to leakage.
 at 45-nm node, leakage power consumes 60% of an
ICs total power.
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ITRS: International Technology Roadmap for Semiconductors
INCREASE DESIGN PERFORMANCE
AND SIDE EFFECTS.

Using new Materials:
Low-k dielectrics.
 Copper.


Using new techniques:
Smaller geometries.
 Lower supply voltage, power dissipation is proportional
to (VDD)^2.
 Lower transistor threshold voltage, VTH.

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Side effects:

Leakage/Static power.
Sub-threshold leakage.
 Gate leakage.
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DRAMATIC SIDE EFFECT ON LEAKAGE
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FACING LOW-POWER SIDE EFFECTS
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MOST POPULAR TECHNIQUES
FOR LOW-POWER-DESIGN
Clock gating.
 Power-aware memories.
 Multi-threshold design.
 Multi-voltage design.
 Power gating.
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CLOCK GATING:
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Simple concept :

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Simple implementation:
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If you don’t need a clock running, shut it down.
Now synthesis tools can automatically do it.
Two popular methods:

Local


Using clock-gating cell: replacing feedback multiplexer.
Global

Turn of the clock to the whole block.
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LOCAL AND GLOBAL CLOCK-GATING
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POWER-AWARE MEMORIES
Effective for lowering both, dynamic power and
leakage power.
 Techniques:

Simple concept: shut down segments of memory
array when they are not in use.
 Multi-mode power.
 Dual-function memories.
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MULTI-THRESHOLD DESIGN :
Addresses leakage power mainly.
 Basic requirements are different threshold
voltage libraries of the same cell’s functionality,
and a power-aware implementation tool.
 Threshold voltage libraries:

Standard/nominal library.
 High-speed library.
 Low-power library.

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Nonlinear relationship:
High threshold voltage slower but less leakage.
 Low threshold voltage faster but leak.
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MULTI-VOLTAGE DESIGN:
Helps designers control dynamic power.
 Critical paths/blocks get access to max voltage.
 Reduce the voltage to Less power-hungry blocks.
 Using level-shifters between blocks with different
voltages.
 Simple concept but complex implementation.
 EDA tools helps with implementation but RTL
problem appears.
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POWER GATING/MTCMOS
Complex technique but very promising.
 Shutdown blocks in design when are not in use.
 Power controller design starts at RTL.
 Techniques:

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Fine-grained: switch transistor between ground and
each gate.
Coarse-grained: using power-switch network.
Medium-grained: a compromise between two
techniques.
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POWER-GATING TRANSISTORS
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REDUCING LEAKAGE USING DIFFERENT
TECHNIQUES
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EDA – ELECTRONIC DESIGN AUTOMATION
Category of tools for designing and producing
electronic systems.
 help designers implement low-power-design
techniques.
 Cadence’s CPF-Common power format.

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A few small EDA companies.
Accellera’s UPF-Unified power format.

Synopsys, Mentor, Magma.
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CONCLUSION
The EDA industry still has much work to do
before it can solve the power problem.
 Designers must become familiar with a mix of
low-power-design techniques.
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