Download CMOS Device Model

HW2
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2.3-3
2.3-5
2.4-4
2.4-6
3.1-4 (Also, use google scholar to find one or two well cited papers on symmetric
models of MOSFET, and quickly study them.)
3.2-3
3.3-1
Q: Given a NMOST with VB=VS=0 and V_GS =constant >V_T+0.1V, when V_D is
gradually increased from 0 to VDD >> V_GS, how does C_GD vary with V_D? How
much total charge goes into or leave the gate terminal?
Q: In a scenario similar to last question, examine how C_DB changes as V_D is
varied from 0 to VDD=4phi. Let mj =mjsw = 0.5 and phi=phi_0=const. For faster
operation, should you use a larger V_D or smaller V_D?
Q: Assume level 1 model, hand sketch gm, r_ds and g_ds as V_D changes.
CMOS Device Model
• Objective
– Hand calculations for analog design
– Non-idealities and their effects
– Efficient and accurate simulation
• CMOS transistor models
– Large signal model
– Small signal model
– Simulation model
– Noise model
Large Signal Model
• Nonlinear equations for solving dc values of
device currents, given voltages
• Level 1: Shichman-Hodges (VT, K', g, l, f, and
NSUB)
• Level 2: with second-order effects (varying
channel charge, short-channel, weak inversion,
varying surface mobility, etc.)
• Level 3: Semi-empirical short-channel model
• Level 4: BSIM models. Based on automatically
generated parameters from a process
characterization. Good weak-strong inversion
transition.
Device is symmetric.
Higher voltage side is drain, lower voltage side is source.
BSIM5 and PSP models will enforce this symmetry.
Transconductance when VDS is small
Transconductance when VDS is small
Voltage controlled resistor and attenuator
Non-uniform channel potential
non-uniform gate-substrate voltage
and non-uniform threshold voltage
Q( x)  WCox vGS  v( x)  VTH 
Good for VDS
<VGS-VTH
After that, ID
become saturated.
dv( x)
dx
dv( x)
iD  WCox vGS  v( x)  VTH  n
dx
1
W
2

iD  nCox  2(vGS  VTH )vDS  vDS
2
L
i  Q  vel ;
vel   n
ron 
1
W
nCox  vGS  VT 
L
Pro: voltage control of resistivity.
Con: nonlinear resistor.
MOST Regions of Operation
• Cut-off, or non-conducting: vGS <VT
– iD=0
• Conducting: vGS >=VT
– Saturation: vDS > vGS – VT
iD
μCoxW

(vGS - VT )2
2L
– Triode or linear or ohmic or non-saturation: vDS <= vGS
– VT
μCoxW
v
iD 
((vGS  VT )vDS 
)
L
2
2
DS
With channel length modulation
iD
μCoxW
2

(vGS - VT ) ( 1  λvDS )
2L
VT  VT 0  g ( 2|φ f |  |v BS| μCoxW
W
 
 K'
L
L
2|φ f | )
Capacitors Of The Mosfet
C2  Weff ( L  2 LD )Cox  Weff ( Leff )Cox
C1  C3  (Weff )( LD )Cox  (CGXO)Weff
CBD and CBS include both the diffusion-bulk
junction capacitance as well as the side wall
junction capacitance. They are highly nonlinear
in bias voltages.
C4 is the capacitance between the channel and
the bulk. It is highly nonlinear and depends on
the operation of the device. C4 is not
measurable from terminals.
C5  (CGBO) Leff / 2
Gate related capacitances
Transistor in off state :
CGB  C2  2C5  (Weff )( Leff )Cox  (CGBO) Leff
CGS  C1  Cox ( LD )(Weff )  CGSO(Weff )
CGD  C3  Cox ( LD )(Weff )  CGDO(Weff )
Transistor in saturation state :
CGB  2C5  (CGBO) Leff
CGS  C1  2 C2  Cox LD (Weff )  2 Cox ( Leff )(Weff )
3
3
 CGSO(Weff )  2 Cox ( Leff )(Weff )
3
CGD  C3  Cox ( LD )(Weff )  CGDO(Weff )
Transistor in triode region :
CGB  2C5  (CGBO) Leff
CGS  C1  0.5C2  Cox LD (Weff )  0.5Cox ( Leff )(Weff )
 CGSO(Weff )  0.5Cox ( Leff )(Weff )
CGD  C3  0.5C2  Cox ( LD )(Weff )  0.5Cox ( Leff )(Weff )
 CGDO(Weff )  0.5Cox ( Leff )(Weff )
Small
signal
model
Typically: VDB, VSB are in such a way that there is
a reversely biased pn junction.
Therefore:
iD
gm 
vGS
gbd ≈ gbs ≈ 0
at quiescent point
g mb  g mbs
iD
g ds 
vDS
iD

vBS
at quiescent point
at quiescent point
In saturation:
g m  2CoxW / L I D (1  lVDS )  2CoxW / L I D
 iD
 iD
g mbs 
 
vSB
 VT
But iD   iD
VT
vGS
 VT 


 vSB 
 VT 
g
  g m
g mbs  g m 
 g m
1/ 2
2(2 fF  VSB )
 vSB 
I Dl
g ds  g o 
 I Dl
1  lVDS
2 CoxW
2 I D 2CoxW
gm 
ID 

VEB  g do
L
VEB
L
CGD  CGDO *Weff
g mbs  g m
1
1


g ds I D l
2
CGS  Cox ( Leff )(Weff )
3
CSB  CJ * Asource
 CJSW * Psource
CGB  CGBO * Leff
CDB  CJ * Adrain
 CJSW * Pdrain
Example spice parameter
In non-saturation region
gm 
CoxW
L
g mbs  
g ds 
CoxW
L
VDS
CoxW
L
very small
VDS
(VGS  VT  VDS ) 
CoxW
(VGS  VT )
L
 g m in saturation
High Frequency Figures of Merit wT
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AC current source input to G
AC short S, D, B to gnd
Measure AC drain current output
Calculate current gain
Find frequency at which current gain = 1.
Ignore rs and rd,  Cbs, Cbd, gds, gbs, gbd all have
zero voltage drop and hence zero current
• Vgs = Iin /jw(Cgs+Cgb+Cgd) ≈ Iin /jw(Cgs+Cgd)
• Io = − (gm − jwCgd)Vgs ≈ − gm Iin /jw(Cgs+Cgd)
• |Io/Iin| ≈ gm/w(Cgs+Cgd)
• At wT, current gain =1
• wT ≈ gm/(Cgs+Cgd)≈ gm/Cgs
• or
High Frequency Figures of Merit wmax
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AC current source input to G
AC short S, B to gnd
Measure AC power into the gate
Assume complex conjugate load
Compute max power delivered by the transistor
Find maximum power gain
Find frequency at which power gain = 1.
BSIM models
• Non-uniform charge density
• Band bending due to non-uniform gate voltage
• Non-uniform threshold voltage
– Non-uniform channel doping, x, y, z
– Short channel effects
• Charge sharing
• Drain-induced barrier lowering (DIBL)
– Narrow channel effects
– Temperature dependence
• Mobility change due to temp, field (x, y)
• Source, drain, gate, bulk resistances
“Short Channel” Effects
• VTH decreases for small L
– Large offset for diff pairs with small L
• Mobility reduction:
– Velocity saturation
– Vertical field (small tox=6.5nm)
– Reduced gm: increases slower than root-ID
Threshold Voltage VTH
• Strong function of L
– Use long channel for VTH matching
– But this increases cap and decreases speed
• Process variations
– Run-to-run
– How to characterize?
– Slow/nominal/fast
– Both worst-case & optimistic
Effect of Velocity Saturation
• Velocity ≈ mobility * field
• Field reaches maximum Emax
– (Vgs-Vt)/L reaches ESAT
• gm become saturated:
– gm ≈ ½nCoxW*ESAT
• But Cgs still 2/3 WL Cox
• wT ≈ gm/Cgs = ¾ nESAT /L
• No longer ~ 1/L^2
Threshold Reduction
• When channel is short, effect of Vd extends to S
• Cause barrier to drop, i.e. Vth to drop
• Greatly affects sub-threshold current: 26 mV Vth
drop  current * e
• 100~200 mV Vth drop due to Vd not uncommon
 100’s or 1000 times current increase
• Use lower density active near gate but higher
density for contacts
Other effects
• Temperature variation
• Normal-Field Mobility Degradation
• Substrate current
– Very nonlinear in Vd
• Drain to source leakage current at Vgs=0
– Big concern for static power
• Gate leakage currents
– Hot electron
– Tunneling
– Very nonlineary
• Transit Time Effects
Consequences for Design
• SPICE (HSPICE or Spectre)
– BSIM3, BSIM4 models
– Accurate but inappropriate for hand analysis
– Verification (& optimization)
• Design:
– Small signal parameter design space:
• gm, CL
• gm/ID, ID
• Av0= gmro
(speed, noise)
(power, output range, speed)
(gain)
– Device geometries from SPICE (table, graph);
– may require iteration (e.g. CGS)
Intrinsic voltage gain of MOSFET
Sweep V1
Measure vgs
Intrinsic voltage gain = gm/go = Dvds/Dvgs for constant Id
Intrinsic voltage gain of MOSFET
Sweep V1
Measure vgs
+
+
Intrinsic voltage gain = gm/go = Dvds/Dvgs for constant Id
Transconductance when VDS is small
Effect of changing VDS for a large VGS
Effect of changing VDS for a given VGS
Effect of changing VDS for a given VGS
Effect of changing VDS for various VGS
VGS<=VT
Effect of changing VDS for various VGS
Effect of changing VDS for various VGS