Download Towards Developing a Standard for

Towards Developing a Standard for
Data Input/Output Format for PDN
Modeling & Simulation Tools
( IEEE TC-12 Subcommittee )
compiled by
Ravi Kaw
(Agilent Technologies)
Contributors
Andreas Cangellaris (UIUC)
Madhavan Swaminathan (GIT)
Jiayuan Fang (Sigrity Inc)
Ravi Kaw (Agilent Tech)
Ching Chao Huang (Optimal Corp)
Zhiping Yang (Cisco)
Om Mandhana (Freescale Semiconductors)
Istvan Novak (Sun Microsystems)
Larry Smith (Sun Microsystems)
Alina Deutsch (IBM)
George Katopis (IBM)
Moises Cases (IBM)
December 1, 2004
1
SCOPE
The scope of this activity is limited to the following:• Modeling Tool(s)
• Simulation Tool(s)
• Metrics for checking ‘effectiveness of design’.
• Methodology
• Define Data-IN standard and Data-OUT standard for modeling and simulation tools
Only the last item above refers to standards. Others are included to define the context within which these standards
play a role. The attempt is to capture various facets of the issues involved, make suggestions for improvements of
tools, and suggest a few methodologies that work; however, none of these can be called standards.
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INTRODUCTION
The IEEE TC-12 sub-committee took upon itself the task of exploring the PDN design environment and suggest
standards where necessary. The idea is to explore all aspects of PDN design and verification, and propose
standards only where necessary, while leaving maximum flexibility to CAD vendors and their customers. A few
standards have been proposed and these are referred to in the text that follows. The same have been compiled in
the appendices at the end of this document. Whenever there appears to be a need for a standard, an indicator (F) is
used next to the item.
It is obvious that a lot of work needs to be done to develop new tools and these future needs have been pointed out
wherever appropriate. Appendix-3 places special emphasis on this.
This document is work-in-progress. Its improvement depends upon the input from everyone involved in this craft.
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PDN Classification
In this document the following nomenclature is used. It is generally observed that engineers in various areas of this
art refer to the same item with different names, which causes confusion. We suggest this nomenclature to avoid
confusion :Whenever noted otherwise, P refers to power like VDD etc, and G refers to ground like GND etc.
• Core Power – PDN (power distribution network)
Its physical contents extend from the core switching networks and P/G grid that reside inside an integrated circuit,
package P/G for core, core P/G network on PCB, and VRM. Sockets and bypass caps on-chip, on-package, and
on-PCB are also included. Occasionally these core P/G planes act as reference planes for some signals, and
therefore may include these signals.
• IO Power - PDN generally includes SDN (signal nets)
Its physical contents extend from the chip-IO’s (including their P/G), including their on-chip bypass caps,
interconnections/redistributions, package and PCB PDN/SDN, and VRM. Sockets, connectors, and bypass caps at
all stages are also included.
• Generic Names It is obvious that both classifications shown above can be either pure PDN or PDN+SDN. In this sense it is best to
use a generic type of classification only; i.e. PDN only, OR PDN+SDN.
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User Profiles
The users of these data and tools can be broadly categorized under three groups:
1. People designing chips/packages only (silicon vendors)
2. People designing application boards only (IC users)
3. People having access and control over the whole chain, such as large OEMs designing and using their own silicon
(they can do chip/package/board co-design)
The data requirements of each of these categories can be different.
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Core PDN
The elements of Core PDN involve the following:1. On-chip switching circuits (RTL Information and test vectors provided by user)
2. On-chip bypass (data provided by user)
3. On-chip P/G grid (data provided in GDS format)
4. Package P/G net and bypass caps
5. PCB P/G structures supporting the core P/G, including bypassing schemes
6. VRM(s)
The on-chip switching activity depends on the circuit type, the logic vectors used, etc. Different companies handle it
differently. Therefore it is preferred that this be provided by the user. Some tools use the core test-vectors as a
starting point. Core loading is best described as net by net resistance (F). This can be condensed for the entire core
or divided by circuit blocks. Some vendors use statistical models as well. Others have proposed the use of a
gaussian current pulse.
caps (values and location) should also be supplied by users. This should include non-switching gates that act as
native bypass caps, and that is also switching pattern sensitive.
The on-chip P/G grid can be modeled as an RC circuit or RLC circuit or a more comprehensive EM based broadband
circuit (tool development effort is required for some of this - see sppendix-3). Three commercial tools offer modeling
capability of this structure with varying degrees of sophistication (Ref: Sigrity, Apache, Ansoft).
Package P/G nets can be modeled with several commercial tools available now. The input file for modeling may be
available in one of the many standard formats (like Allegro from Cadence). Most modeling tools are based upon a
single frequency extraction. Modeling tools need some upgrades and these have been listed later in this document.
At least two modeling tools can create wideband models of the package and the PCB, either separately or together.
One preferred methodology suggests the use of separate models for each package and the PC Board that can be
put together in the simulator (see appendix-2).
Output data of impedance vs frequency can be based on measurements also, although this can capture only a
limited condition of logic activity. Still this is a good starting point. The output should be compatible with popular
simulators like Spice, IBIS, etc. In case of large data file, macro-models may be used.
One suggested format for the extracted data is proposed by Dr. Fang (appendix-1)
Metrics for evaluation of Core Power
Metric for this is Impedance vs frequency. (a suggested format can be found in appendix-1)
OR voltage-ripple + current signature
6
(Appendix-5 describes a method for coming up with Z vs. f )
7
IO PDN + SDN
The elements of IO PDN involve the following:1. On-chip switching circuits (IOs). This can in the form of driver models or an extracted net that captures the related
IO structures as well, with pulse input. These files can become voluminous. One fix is to create macro-models that
can support the various nuances of the drivers, like variable drive strengths, etc. A key item in these extracted
models is the pre-emphasis. That should be included as well. Some of this sophisticated macro-modeling is still
being developed at university level, and has yet to be commercialized.
2. On-chip bypass - both add-on and native (supporting the IOs), extracted by user.
3. On-chip P/G grid (supporting the IOs)
4. Package P/G and IO nets, plus bypass caps.
5. PCB P/G structures, signal nets, and bypass schemes used.
6. Connectors for signal nets on the PCB, and for P/G (if used).
7. Far end package IO structures and input circuitry of the receiver circuit. This should include the terminations, the
ESD network, etc. Again a macro-model may be useful substitute of a large extracted net.
8. VRM(s)
Most comments listed under core-PDN apply to this as well.
The IO power and signals interact non-linearly via the drivers, and should preferably be modeled and simulated
simultaneously. Both frequency domain and time domain simulations are required.
It is also preferable to have broadband models for both PDN and SDN structures.
Metrics for Evaluation (IO Power)
Eye Diagram.
The standard for this is best described by the user, depending on their requirements.
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Logic Failure:
This has been suggested by some, but is not commonly used.
Delay: This has been suggested by some, but is not commonly used.
Impedance vs frequency (F)
This is a favorite among many users for IO PDN also.
(a suggested format can be found in appendix-1)
(Appendix-5 describes a method for coming up with Z vs. f )
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Desirable Common Basic Features for both PDNs
PDN dc resistance calculator
The terminals for this should be defined by the user. This may simply condense all the sources (solder-bumps or
wire-bonds) and all the sinks (balls or pins) into a two terminal net for each power and ground net, OR break them
into groups specific to some circuit blocks OR simply group them into Geographical regions. It should be noted that
DC resistance is not modeled by every modeling tool. For such tools, sometimes one can approximate DC
conditions it by choosing a frequency at which the skin depth is equal to half of trace thickness. Of course this is not
representative of the many via sizes or even the plane thickness, which may be different from the trace thickness.
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Methodology
•Mostly user defined
We have three examples of these in appendices - 2, 4, and 6. No preferences are implied here and these examples
are presented for the sake of completeness.
The first one (by Om Mandhana) uses Sigrity's tool to model each package as well as the PC Board separately. Then
it combines them in the simulation tool.
The second one (by Madhawan Swaminathan) uses Georgia-Tech's proprietary software.
The third one is a proposal (by Chin Chao Huang).
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Proposed Requirements of Modeling Tool(s)
•Can download stack-up info from various design tools.
• Support rapid extraction of frequency dependent impedance of multiple P/G plane stack-up for quick PDN only
analysis, AND “P/G+signal” extraction for accurate PDN+SDN analysis.
• Support P/G pin/via “condensation/merging” when needed.
• Supports de-embedding of reference nodes inside a structure that do not need to be connected to the global
ground; e.g: bypass cap nodes.
• Accept incorporation of different electrical models for decoupling caps
• Generate frequency dependent impedance for all structures (IC, Package, and PCB) to include PDN+SDN for IO
power.
• Output compatibility with network simulation tools.
• Model PCBs, Packages, On-chip P/G Grid, Sockets, Connectors, VRMs (could be several tools)
• Multi-port macro-model generation capability to reduce complexity
• Calculate bandwidth of validity for the user. Provide methods to enhance it.
•Modeling tools must be flexible enough to model portions of a system (pkg by pkg or portions of PCB or pkg+small
portion of PCB around it), so that models of either can be used elsewhere.
• Modeling tools should deliver output that can be used in a simulation engine elsewhere (outside the tool’s
framework) in a standard format.
• Modeling tools should be able to convert between S,Y,Z,ABCD formats, and also from frequency dependent
model parameters into equivalent time domain sub-circuits without causality (etc) problems.
• Sensitivity analysis based on tolerances of geometry and material properties would be helpful in a combined
modeling/simulation tool.
• Incorporate effect of trace edge shape.
• Use actual shape of via structures.
• Include all couplings (e.g: between traces and between vias, etc.)
• Include effective and accurate ways to account for ‘holy’ planes, splits, etc.
Proposed Requirements of Simulation Tools
•Fast and reasonably accurate nonlinear simulators to handle large busses along with their P/G network
(PDN+SDN).
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• Accept lumped as well as behavioral (Macro-models) models compatible with IBIS-4. Pre-emphasis would be
helpful and often quite necessary.
• Support both time-domain and frequency-domain analysis with built-in software for conversion of waveforms
between the two.
• Should be able to handle required bandwidth. Allow user to test for passivity and bandwidth.
• Somewhere down the road we need statistical results because of the wide variations in most structural details.
• With the shrinking noise margins in presence of structures whose geometrical tolerances are rather large (5 to
10%), statistical simulation methods are needed. These may require some development effort as well as
commercialization.
• Simulation tools should also be able to convert between S,Y,Z,ABCD formats, and also from frequency
dependent model parameters into equivalent time domain sub-circuits without causality (etc) problems.
APPENDIX-1
Standard Interface Format for Power Integrity Analysis
on Printed Circuit Boards
Jiayuan Fang
13
Sigrity, Inc.
October 5, 2004
Objectives:
Establish a standard that interfaces between chip/package vendors and printed circuit
board vendors for the power integrity closure of system level board
I. Chip/package vendors provide board vendors the following specification and information:
I.1
For each power net of the chip, the required frequency-dependent target
impedance profile looking into the board.
It serves as the specification to the board. It is the impedance measured at
the solder pads of the board, with all the pads of the power net regarded as
one node, and all the pads of the corresponding ground net regarded as
the other node.
The target impedance can be specified in a piece-wise linear data format,
composed of a number of pairs of data. The first data of the pair is the
frequency; the second data of the pair is the absolute value of the
impedance at the frequency. There should be at least two pairs of data in a
target impedance profile, covering the frequency range the impedance is to
be met.
I.2
For each power net of the chip, an equivalent circuit model (in SPICE format) for
the on-chip power delivery system looking into the chip from chip-package
interface
This SPICE circuit model of the on-chip power system is a simplified model
for the purpose of power integrity analysis on board. It should include onchip capacitors and average resistive loading of the chip. It may also
include other parasitic effects of on-chip power delivery systems. As an
example, a simple circuit model of an on-chip power system consists of a
capacitor in parallel with a resistor, represented in SPICE syntax.
The SPICE circuit model only contains linear passive components. That is,
it does not contain non-linear elements or source elements. Reasons for
such specifications are as follows:
(1) The target impedance that a board vendor tries to achieve is under the
condition that the board is loaded with various chips on the board.
Each power net of each chip is modeled by the on-chip SPICE circuit
provided by the corresponding chip vendor. Since the results to be
looked at are in the frequency-domain, all the circuit elements
considered should be linear.
(2) To meet the target impedances of a board, there is no need of the
source information in the on-chip circuit model.
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I.3
For each power net of the package, a broadband SPICE model of the package
power delivery system.
The broadband SPICE model is a two port model with one port on the die
side and the other port on the board side. It includes the entire package
structure from C4 or wirebonds to solder balls. On either the die side or
the board side, all the pads of the power net are regarded as one end of the
port, and all the pads of the corresponding ground net are regarded as the
other end of the port.
The broadband SPICE model can be either in S-parameter touchstone
format or lumped equivalent circuits in SPICE syntax.
If the broadband SPICE model of the package is provided in S-parameter
touchstone format, it should contain large enough frequency range, fine
enough frequency resolution, and low reference impedance.
(1) The lowest frequency should not be higher than 1 kHz. The highest
frequency should not be lower than the highest frequency in the target
impedance profile.
(2) Under 1 MHz, there should be at least two frequency points per decade.
Above 1 MHz, the frequency interval should not exceed 10 MHz.
(3) The reference impedance of 0.1 Ohm is preferred rather than the
conventional default of 50 Ohm. Since package power delivery
systems are typically of low input impedances, low reference
impedance will increase the data resolution in the S-parameter
representation of the power delivery system.
If the broadband SPICE model of the package is provided in lumped
equivalent circuit format, the maximum frequency of the circuit model
should be specified if the circuit model is converted from N-port network
parameters.
Information provided in items I.2 and I.3 serve as the power and ground loading of
the chip/package onto the board.
II. Board vendors provide chip/package vendors:
II.1 For each chip on the board, and for each power net, a broadband SPICE model of
the impedance looking into the board.
Here, the impedance obtained is under the condition that the board is
loaded with the load information provided in I.2 and I.3, except the load of
the power net of the chip for which the impedance is provided.
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This SPICE model of the board confirms whether the board design meets
the specification. It can also be used for the power integrity analysis on
the chip and/or package levels.
The broadband SPICE model of the impedance can either be in one-port Sparameter touchstone format or lumped equivalent circuits in SPICE
syntax.
If the broadband SPICE model of the impedance is provided in S-parameter
touchstone format, it should contain large enough frequency range, fine
enough frequency resolution, and low reference impedance.
(1) The lowest frequency should not be higher than 1 kHz. The highest
frequency should not be lower than the highest frequency in the target
impedance profile.
(2) Under 1 MHz, there should be at least two frequency points per decade.
Above 1 MHz, the frequency interval should not exceed 10 MHz.
(3) The reference impedance of 0.1 Ohm is preferred rather than the
conventional default of 50 Ohm.
If the broadband SPICE model of the impedance is provided in lumped
equivalent circuit format, the maximum frequency of the circuit model
should be specified if the circuit model is converted from N-port network
parameters.
Note:
The proposal above is frequency-domain oriented based on maximum target
impedance. An alternative time-domain oriented standard can also be defined which is based
on maximum voltage ripples, and chip vendors are required to provide a current signature of
for each power net of each chip.
The above interface is for the purpose of power integrity analysis on the board level.
Some approximations are made for the convenience of board level simulation, such as
snapping all the power net pads on a package into one node. To have more accurate analysis
of the power delivery systems, it is sometimes more desirable to have chip-package, packageboard, or chip-package-board co-simulation.
APPENDIX-2
Modeling, Simulation and Analysis Methodology for Power Distribution Networks of
High Performance Digital Systems
Om P. Mandhana, Freescale Semiconductor, Austin, TX, Jin Zhao, Sigrity Inc., CA
16
The efficient methodology for modeling, simulation and analysis of power distribution
network (PDN) of high performance computer system is critically important for the design and
development of products with reduced cycle time. The PDN, in general, consist of printed circuit
boards with ICs and microprocessor packages, vias and predefined locations for decoupling
capacitors on the PCB and packages. An iterative method is commonly used to find the optimum
number and values of the parameters (ESR, ESL and C) of the decoupling capacitor to be placed
on the PCB and the packages for designing the PDN of reduced noise.
Several commercial field solver tools are currently available for the purpose of modeling,
simulation and analysis for efficient design of the PDN with reduced noise. Based on the
simulation using commercially available field solvers, the PDN characteristics are described in
terms of the N-port scattering-parameter (S-parameter) matrix, or impedance-parameter (Zparameter)
matrix or admittance-parameter (Y-parameter) matrix. Some of these field solvers
efficiently convert the S/Z/Y parameters in SPICE compatible model valid over a wide
frequency range.
For the efficient PDN modeling, simulation and analysis a methodology developed using
the ABCD matrix representation of the components of the PDN was presented in ECTC 2004 as
a paper by Om P. Mandhana of Freescale Semiconductor and Jin Zhao of Sigrity Inc. The key
features of the methodology presented in the paper can be summarized as follows:
(a) Using commercially available field solver, model and simulate the PCB including the
VRM model to generate impedance matrix in touchstone format
(b) Using commercially available field solver, model and simulate the IC/microprocessor
Package(s) to generate S/Z-matrix in touchstone format
(c) Convert the S-parameters of the PCB and packages to ABCD-parameters
(d) Express the Core/Die parameters in terms of the ABCD parameters
(e) Combine/cascade the ABCD parameters of the PCB, Packages and Core/Die
(f) Compute the total input impedance at the microprocessor location, using the resultant
ABCD parameters of step (e)
(g) Add decoupling capacitor parameters on the PCB/Package with target frequency to be
eliminated from the plot of the computed input impedance of step (f)
(h) Repeat steps (a)-(g) until the total input impedance magnitude at the PDN
components is close to the specified target impedance.
This method can be used effectively for the design of a PDN with one/two
microprocessor packages mounted on the PCB. However, adding different number of decoupling
capacitors around each microprocessor on the board and performing iterative simulation of the
PDN takes large time for the optimum design of the noise-free PDN.
We propose a more efficient approach to use impedance matrix techniques of combining
different PDN blocks (PCB, Packages, DECAPS, Core/Die, and VRMs) together to generate a
resultant input impedance magnitude profile close to the desired target input impedance over a
frequency range of interest.
An outline of this impedance matrix approach is described below:
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(a) Using commercially available field solver, generate Z-parameter matrix for the PCB
board, package and on-die interconnection, in touchstone format. The ports for the
DECAPs VRMs and ICs can be defined.
(b) Analytically, combine the Z-parameters of the PCB, Packages and Core/Die through
network connection techniques and generate input impedance profile to compare the
results with target input impedance specifications
(c) Perform the analysis with different DECAP parameters, connected to the system and
evaluate the performance of the power delivery system
(d) Repeat steps (c) until the input impedance magnitude is close to the specified target
impedance.
We suggest that the simulation data for the purpose of exchanging the information
between the customers and vendors can be in touchstone format. However, the reference
impedance value used by the field solvers for different components of the PDN (PCB, Packages)
should be different and not always 50 Ohm as a standard.
APPENDIX-3
Please see the attached power-point by Andreas Cangellaris.
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APPENDIX-4
Modeling of Power Distribution Networks
Madhavan Swaminathan
Professor and Deputy Director, NSF-ERC on SOP Technology
School of Electrical and Computer Engineering
Georgia Tech
Atlanta, GA 30332-0250
The goal is to develop methodologies that can standardize the modeling and analysis of power
distribution networks. Though numerous numerical methods are available for modeling,
ultimately standardized interfaces and formats are necessary so that the models can be ported
between the various tools available. To this end, it would be appropriate to use Spice as the
simulator for the simulation of power supply noise. This has many advantages namely, a) spice
formats are well known, b) existing libraries of models can be used, c) IBIS and other nonlinear model libraries can be used and d) it becomes easy to standardize interfaces since the
formats are well known. However, a limitation of Spice is the inability to simulate large size
networks, which are typical in power distribution. Hence the following modeling methods and
methodologies are proposed:i)
Modeling of the linear network consisting of planes, decoupling capacitors, vias and other
power distribution interconnect structures using an EM based numerical method. Since, the
target impedance is a measure of the performance, the output are impedance parameters
varying as a function of frequency. This could be 1-port, 2-port or n-port parameters, but it is
advantageous to limit the number of ports to <32 for ease of use. The numerical method we
have developed is based on the transmission matrix method that uses the ABCD parameters
to generate impedance parameters at specific nodes for large size problems (20 layers with
1M nodes). At this stage, the user optimizes the design based on the impedance parameters
either by changing the layout or the placement of decoupling capacitors.
ii)
Conversion of the impedance parameters (as a function of frequency) into a spice-netlist.
This becomes advantageous for two reasons namely, a) the problem size has been reduced by
reducing the number of nodes in the circuit and b) other spice models can be connected to the
power distribution macro-model. We have developed a rational function based interpolation
scheme that automatically generates a spice netlist.
iii)
Power supply noise is dependent on the return currents on the planes. Hence, the interconnect
models of transmission lines are very important in predicting power supply noise. Since, the
power distribution models have been ported into spice, spice models of transmission lines
can be developed and connected to the power supply models in spice. A very good
transmission line model available in Hspice is the W-Element model, using which 4-port
models of transmission lines can be developed. We have developed a method that
automatically develops these transmission line models from TDR measurements of
transmission lines. Another option is to use your favorite modeling technique for
transmission lines, developing a W-element model and connecting it to the power
distribution model in Spice.
iv)
The signature and amplitude of power supply noise is dependent on the non-linearity of the
drivers. IBIS models do not capture the non-linear effects well. Transistor level device
models of drivers, though accurate, can take a long time to simulate in Spice. Another option
19
is the development of macro-models for the I/O drivers in a Spice format that provide the
necessary accuracy at minimum CPU time. We have developed a methodology for the
modeling of non-linear I/O drivers that automatically generates a spice netlist from transistor
level driver models. These models can be directly connected to the other models available in
spice.
v)
Ultimately, the current signatures of the drivers are necessary, if the driver models are
unavailable. This can be obtained only from measurements. We have developed a method
that extracts noise current signatures from measurements and generates a spice netlist. The
spice netlist provides a good representation of the current waveform and can be used to
simulate power supply noise by connecting the current model with the rest of the available
models.
The architecture of the tools that we have developed are shown in Figure 1.
Cadence
Chip FDTD
Pkg TMM
LTI Macro.
BEMP
Nonlin
Macro
Meas.
Based
Spice
Statist
ical
20
APPENDIX-5
Some starting points on how to generate a target impedance for a board.
by Larry Smith
Target Impedance = Vdd * tolerance / transient_current
Start with tolerance = 5% (0.05 in above equation).
Start with transient_current = 50% of total current.
Calculate total current from VRM Watts/Vdd.
Every board designer has this information or else they could not size
the VRM power supply. Some people are more comfortable with 3%
tolerance on Vdd.
With experience, the percentage of current transient should be adjusted.
Processors with no energy management tend to draw almost constant
current so the transient current might be 10% or 20%. Processors with a
lot of energy management might take 80% or 90% current transients. DRam
DIMMs tend to take about 85% transients. Differential signal supplies
tend to draw constant current so 20% transient current would be
sufficient. The product designer must make adjustments in this area
with knowledge of the product. 50% current transient is a good starting
point unless you are really conservative, then use 100%
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APPENDIX-6
See power-point by Ching Chao Huang.
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