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Computing Systems
Basic arithmetic for computers
claudio.talarico@mail.ewu.edu
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Numbers
ƒ
Bit patterns have no inherent meaning
ƒ conventions define relationship between bits and numbers
ƒ
Numbers can be represented in any base
n
∑ digiti × basei
i =0
ƒ
Binary numbers (base 2)
ƒ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...
ƒ decimal: 0...2n-1
ƒ
Of course it gets more complicated:
ƒ negative numbers
ƒ fractions and real numbers
ƒ numbers are finite (overflow)
ƒ
How do we represent negative numbers?
i.e., which bit patterns will represent which numbers?
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Possible Representations
Sign Magnitude
One's Complement Two's Complement
000 = +0
001 = +1
010 = +2
011 = +3
100 = -0
101 = -1
110 = -2
111 = -3
000 = +0
001 = +1
010 = +2
011 = +3
100 = -3
101 = -2
110 = -1
111 = -0
000 = +0
001 = +1
010 = +2
011 = +3
100 = -4
101 = -3
110 = -2
111 = -1
ƒ Issues: balance, number of zeros, ease of operations
ƒ Which one is best? Why?
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Two’s complement format
… -4 -3 -2 -1 0 1 2 3 4 …
-2
1110
-1
1111
0
0000
1
0001
2
0010
3
0011
-3
1101
4
0100
-4
1100
5
0101
1011
-5
1010
-6 1001
-7
1000
-8
0111
7
0110
6
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Two’s complement operations
ƒ
Negating a two’s complement number: invert all bits and add 1
ƒ remember: “negate” and “invert” are quite different !
ƒ The sum of a number and its inverted representation must be
111….111two, which represent –1
x + x + 1 = 0 ↔ x + x = − 1 ↔ −x = x + 1
ƒ
Converting n bit numbers into numbers with more than n bits:
ƒ copy the most significant bit (the sign bit) into the other bits
0010 Æ 0000 0010
1010
Æ 1111 1010
ƒ Referred as "sign extension"
ƒ MIPS 16 bit immediate gets converted to 32 bits for arithmetic
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Two’s complement
ƒ Two’s complement gets its name from the rule that the
unsigned sum of an n bit number and its negative is 2n
ƒ Thus, the negation of a number x is 2n-x
ƒ adding a number x and its negate considering the bit
patterns as unsigned:
x + x + 1 = (x + x) + 1 =
(2 − 1) + 1 = 2n
n
111…11two
ƒ Negative integers in two’s complement notation look like
large numbers in unsigned notation
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MIPS word is 32 bits long
ƒ 32 bit signed numbers:
0000
0000
0000
...
0111
0111
1000
1000
1000
...
1111
1111
1111
0000 0000 0000 0000 0000 0000 0000two = 0ten
0000 0000 0000 0000 0000 0000 0001two = + 1ten
0000 0000 0000 0000 0000 0000 0010two = + 2ten
1111
1111
0000
0000
0000
1111
1111
0000
0000
0000
1111
1111
0000
0000
0000
1111
1111
0000
0000
0000
1111
1111
0000
0000
0000
1111
1111
0000
0000
0000
1110two
1111two
0000two
0001two
0010two
=
=
=
=
=
+
+
–
–
–
2,147,483,646ten
2,147,483,647ten = 231-1
2,147,483,648ten = -231
2,147,483,647ten
2,147,483,646ten
1111 1111 1111 1111 1111 1111 1101two = – 3ten
1111 1111 1111 1111 1111 1111 1110two = – 2ten
1111 1111 1111 1111 1111 1111 1111two = – 1ten
msb (bit 31)
maxint
minint
lsb (bit 0)
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Addition and subtraction
ƒ Just like in grade school (carry/borrow 1s)
0111
+ 0110
_1101
0111
- 0110
0001
0110
- 0101
0001
ƒ Two's complement operations easy
ƒ subtraction using addition of negative numbers
0111
+ 1010
0001
ƒ Overflow (result too large for finite computer word):
ƒ adding two n-bit numbers does not yield an n-bit number
0111
+ 0001
_1000
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Detecting overflow
ƒ No overflow when adding a positive and a negative
number
ƒ No overflow when signs are the same for subtraction
ƒ Overflow occurs when the value affects the sign:
ƒ overflow when adding two positives yields a negative
ƒ or, adding two negatives gives a positive
ƒ or, subtract a negative from a positive and get a
negative
ƒ or, subtract a positive from a negative and get a
positive
ƒ Consider the operations A + B, and A – B
ƒ Can overflow occur if B is 0 ? cannot occur !
ƒ Can overflow occur if A is 0 ? can occur !
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Effects of overflow
ƒ An exception (interrupt) occurs
ƒ Control jumps to predefined address for exception
ƒ Interrupted address is saved for possible resumption
ƒ Details based on software system / language
ƒ Don't always want to detect overflow
ƒ new MIPS instructions: addu, addiu, subu
ƒ unsigned integers are commonly used for memory
addresses where overflows are ignored
note: addiu still sign-extends!
note: sltu, sltiu for unsigned comparisons
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Division
ƒ Even more complicated than multiplication
ƒ It even offers the opportunity to perform a mathematically
invalid operation: dividing by 0
ƒ Can be accomplished via shifting and addition/subtraction
ƒ It takes more area and time
ƒ There are techniques to speedup the division, we won’t
look at them
ƒ Negative numbers:
ƒ the simplest solution is to remember the signs of the
divisor and dividend and negate the quotient if signs
disagree
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Floating point numbers (a brief look)
ƒ We need a way to represent
ƒ numbers with fractions, e.g., 3.1416
ƒ very small numbers, e.g., .000000001
ƒ very large numbers, e.g., 3.15576 x 109
ƒ solution: scientific representation
ƒ sign, exponent, significand:
(–1)sign x significand x 2E
ƒ more bits for significand gives more accuracy
ƒ more bits for exponent increases range
ƒ A number in scientific notation that has no leading 0s is
called normalized
( −1)sign × 1.xxx ⋅ ⋅ ⋅ xxx × 2 E
(1+fraction)
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Floating point numbers
ƒ A floating point number represent a number in which the
binary point is not fixed
ƒ IEEE 754 floating point standard:
ƒ single precision: (32 bits)
ƒ 1 bit sign, 8 bit exponent, 23 bit fraction
ƒ double precision: (64 bits)
ƒ 1 bit, 11 bit exponent, 52 bit fraction
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IEEE 754 floating-point standard
ƒ Leading “1” bit of significand is implicit
ƒ Exponent is “biased” to make sorting easier
ƒ all 0s is smallest exponent all 1s is largest (almost)
ƒ bias of 127 for single precision and 1023 for double
precision
ƒ summary: (–1)sign × (1+fraction) × 2exponent – bias
ƒ Example:
ƒ decimal: -.75 = - ( ½ + ¼ )
ƒ binary: -.11 = -1.1 x 2-1
ƒ floating point:
ƒ exponent = E + bias = -1+127=126 = 01111110two
ƒ IEEE single precision:
sign
exponent
fraction
1 01111110 10000000000000000000
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IEEE 754 encoding of floating points
Single precision
Double precision
Number
Exponent
Fraction
Exponent
Fraction
0
0
0
0
0
0
nonzero
0
nonzero
+/- denormalized
1 - 254
nonzero
1 - 2046
nonzero
+/- floating point
255
0
2047
0
+/- infinity
255
nonzero
2047
nonzero
NaN
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Floating point complexities
ƒ Operations are somewhat more complicated (see text)
ƒ In addition to overflow we can have “underflow”
ƒ Overflow: a positive exponent too large to fit in the exponent field
ƒ Underflow: a negative exponent too large to fit in the exponent field
ƒ Accuracy can be a big problem
ƒ IEEE 754 keeps two extra bits, guard and round
ƒ four rounding modes
ƒ positive divided by zero yields “infinity”
ƒ zero divide by zero yields “not a number” (NaN)
ƒ other complexities
ƒ Implementing the standard can be tricky
ƒ Not using the standard can be even worse: Pentium bug!
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IEEE 754 encoding
Single precision
Double precision
Number
Exponent
Fraction
Exponent
Fraction
0
0
0
0
0
0
nonzero
0
nonzero
+/- denormilized
1 to 254
nonzero
1 to 2046
nonzero
+/- floating point
255
0
2047
0
+/- infinity
255
nonzero
2047
nonzero
NaN
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Floating point addition/subtraction
To add/sub two floating point numbers:
ƒ Step1. we must align the decimal point of the number with
smaller exponent
ƒ compare the two exponents
ƒ shift the significand of the smaller number to the right by an
amount equal to the difference of the two exponents
ƒ Step 2. add/sub the significands
ƒ Step 3. The sum is not in normalized scientific notation, so we
need to adjust it
ƒ either shifting right the significand and incrementing the
exponent, or shifting left and decrementing the exponent
ƒ Step 4. We must round the number
ƒ add 1 to the least significant bit if the first bit being thrown
away is 1
ƒ Step 5. If necessary re-normalize
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Floating point addition/subtraction
Start
Sign Exponent
Fraction
Sign
Exponent
Fraction
1. Compare the exponents of the two numbers.
Shift the smaller number to the right until its
exponent would match the larger exponent
Small ALU
2. Add the significands
Exponent
difference
0
1
0
1
0
1
3. Normalize the sum, either shifting right and
incrementing the exponent or shifting left
and decrementing the exponent
Shift right
Control
Overflow or
underflow?
Yes
Big ALU
No
0
0
1
Increment or
decrement
1
Exception
4. Round the significand to the appropriate
number of bits
Shift left or right
No
Still normalized?
Rounding hardware
Yes
Sign
Exponent
Fraction
Done
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Accuracy of floating point arithmetic
ƒ Floating-point numbers are often approximations for a
number they can’t really represent
ƒ Rounding requires the hardware to include extra bits in
the calculation
ƒ IEEE 754 always keeps 2 extra bits on the right during
intermediate additions called guard and round
respectively
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Common fallacies
ƒ Floating point addition is associative x + (y+z) = (x+y)+z
ƒ Example:
− 1.5 ten × 10 38 + (1.5 ten × 1038 + 1.0) = −1.5 ten × 1038 + (1.5 ten × 10 38 ) = 0.0
( −1.5 ten × 10 38 + 1.5 ten × 10 38 ) + 1.0 = (0.0 ten ) + 1.0 = 1.0
ƒ Just as a left shift can replace an integer multiply by a power of
2, a right shift is the same as an integer division by a power of 2
(true for unsigned, but not for signed even when we sign extend)
ƒ Example: (shift right by two = divide by 4ten)
-5ten = 1111 1111 1111 1111 1111 1111 1111 1011two
1111 1111 1111 1111 1111 1111 1111 10two = -2ten
It should be –1ten
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Concluding remarks
ƒ Computer arithmetic is constrained by limited precision
ƒ Bit patterns have no inherent meaning (side effect of the
stored-program concept) but standards do exist
ƒ two’s complement
ƒ IEEE 754 floating point
ƒ Computer instructions determine “meaning” of the bit patterns
ƒ Performance and accuracy are important so there are many
complexities in real machines
ƒ Algorithm choice is important and may lead to hardware
optimizations for both space and time (e.g., multiplication)
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