Download Linköping University Post Print On-Chip Stimulus Generator for Gain,

Linköping University Post Print
On-Chip Stimulus Generator for Gain,
Linearity, and Blocking Profile Test of
Wideband RF Front Ends
Rashad Ramzan, Naveed Ahsan and Jerzy Dabrowski
N.B.: When citing this work, cite the original article.
©2010 IEEE. Personal use of this material is permitted. However, permission to
reprint/republish this material for advertising or promotional purposes or for creating new
collective works for resale or redistribution to servers or lists, or to reuse any copyrighted
component of this work in other works must be obtained from the IEEE.
Rashad Ramzan, Naveed Ahsan and Jerzy Dabrowski, On-Chip Stimulus Generator for Gain,
Linearity, and Blocking Profile Test of Wideband RF Front Ends, 2010, IEEE
TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, (59), 11, 28702876.
http://dx.doi.org/10.1109/TIM.2009.2036454
Postprint available at: Linköping University Electronic Press
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-61314
2870
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 11, NOVEMBER 2010
On-Chip Stimulus Generator for Gain, Linearity, and
Blocking Profile Test of Wideband RF Front Ends
Rashad Ramzan, Member, IEEE, Naveed Ahsan, Member, IEEE, and Jerzy Dabrowski, Member, IEEE
Abstract—This paper presents the design and measurement
of a stimulus generator suitable for on-chip RF test aimed
at gain, 1-dB compression point (CP), and the blocking profile measurement. Implemented in a 90-nm complementary
metal–oxide–semiconductor (CMOS), the generator consists of
two low-noise voltage-controlled ring oscillators (VCOs) and an
adder. It can generate a single- or two-tone signal in a range
of 0.9–5.6 GHz with a tone spacing of 3 MHz to 4.5 GHz and
adjustable output power. The VCOs are based on symmetrically
loaded double-differential delay line architecture. The measured
phase noise is −80 dBc/Hz at an offset frequency of 1 MHz for the
oscillation frequency of 2.4 GHz. A single VCO consumes 26 mW
at 1 GHz while providing −10-dBm power into a 50-Ω load.
The silicon area of the complete test circuit including coupling capacitors is only 0.03 mm2 , while a single VCO occupies
0.012 mm2 . The measured gain, 1-dB CP, and blocking profile of
the wideband receiver using the on-chip stimulus generator are
within ±8%, ±10%, and ±18% of their actual values, respectively. These error values are acceptable for making a pass or fail
decision during production testing.
Index Terms—On-chip RF testing, RF design for testability
(DfT), RF test, stimulus generator, voltage-controlled oscillator
(VCO).
I. I NTRODUCTION
W
IDEBAND RF front ends have the potential to meet
the demands of future multiband and multistandard receivers. The advantage is smaller silicon area and lower power
consumption compared to the solution employing multiple
front ends (one for each band) or a tunable front end for a
group of frequency bands [1]. For the production testing of
such a receiver, a bandwidth of several gigahertz is needed
from the signal source to the on-chip front end under test.
This makes the design of the chip package and printed circuit
board (PCB) transmission lines a challenging task. Due to the
extremely large bandwidth, the use of lumped elements on a
PCB to tune out the parasitics, which is a common practice in
Manuscript received April 30, 2009; revised July 31, 2009; accepted
September 15, 2009. Date of publication July 26, 2010; date of current version
October 13, 2010. The Associate Editor coordinating the review process for this
paper was Dr. Wendy Van Moer.
R. Ramzan was with Linkoping University, 58183 Linkoping, Sweden. He
is now with the Department of Electrical Engineering, National University
of Computer and Emerging Sciences, Islamabad 44000, Pakistan (e-mail:
rashad@ieee.org, rashad.ramzan@nu.edu.pk).
N. Ahsan was with Linkoping University, 58183 Linkoping, Sweden. He is
now with the Advanced Engineering Research Organization, Islamabad 47040,
Pakistan (e-mail: naveed@ieee.org).
J. Dabrowski is with the Electrical Engineering Department, Linkoping
University, 58183 Linkoping, Sweden (e-mail: jdab@isy.liu.se).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIM.2009.2036454
narrow-band designs, is no longer an option. Moreover, the test
methodologies like probe testing used to characterize the circuit
during the design phase are very expensive in volume production in terms of setup time, cost, and complexity. One possible
solution to these problems is the use of on-chip test circuitry
for test measurements. In nanometer CMOS technologies, the
circuit dimensions are small compared to the wavelength of
interest. Therefore, the signals do not suffer from transmission
line effects on a chip.
To test the gain, linearity, and blocking profile of an RF front
end, two voltage-controlled oscillators (VCOs) with a wide
tuning range and an adder with power control are needed. These
components should feature a performance good enough for test,
i.e., a small chip area overhead and low phase noise, but there
is no stringent limit on the power consumption, since the circuit
will be only used during the test mode.
The straightforward approach to build an on-chip oscillator
is to use either an LC-tank-based or delay-cell-based circuit (ring oscillator). LC-tank-based oscillators have excellent
phase noise performance, but the tuning range is usually not
more than 20%–25%, and high-Q inductors are mandatory in
this case. To realize such high-Q inductors, a large chip area and
special enhancements within the CMOS process are needed.
On the other hand, ring oscillators are better suited for onchip integration using a standard CMOS process and occupy
a small chip area that improves both the yield and the cost of
the chip. In-phase and quadrature-phase components can easily
be generated [2]. However, the phase noise performance of ring
oscillators is, in general, poorer compared to LC oscillators.
In this paper, we present a stimulus generation circuit with
a small chip area that achieves a wide tuning range of 0.9–
5.6 GHz, low phase noise, and variable output power. The
core of this circuit is a modified voltage-controlled delay line
(VCDL) capable of providing a wide tuning range and low
phase noise at all oscillation frequencies. This circuit is successfully used to test the gain, 1-dB compression point (CP),
and blocking profile of wideband RF front ends.
The stimulus generation circuit consists of two VCOs, an
adder, coupling capacitors, and switches, as shown in Fig. 1.
Each VCO has nine VCDLs, which are designed such that they
can seamlessly be switched to provide either a five- or nineVCDL ring architecture, thus covering the complete frequency
range of interest. The design and operation of the basic VCDL
is discussed in Section II. The adder circuit is used to generate
two tones with an adjustable output power level while driving
a 50-Ω load. The design of the modified VCDL, VCO, and
adder circuit is discussed in Section III. Section IV presents
the stimulus generator performance in terms of its tuning
0018-9456/$26.00 © 2009 IEEE
RAMZAN et al.: ON-CHIP STIMULUS GENERATOR FOR GAIN, LINEARITY, AND BLOCKING PROFILE TEST
Fig. 1. Block diagram of the wideband radio receiver with on-chip test
stimulus generator.
range, phase noise, dynamic range, and power consumption. In
Section V, a wideband RF front end is demonstrated under test
for the gain, 1-dB CP, and blocking profile using the on-chip
stimulus generator, and the measurement results are compared
with actual values. Section VI concludes with a summary and
some future direction.
II. D ESIGN OF THE BASIC D ELAY L INE (VCDL)
VCOs based on the ring architecture fall in two categories,
i.e., saturated and nonsaturated, according to the behavior of
the delay line transistors. In the nonsaturated-type VCO, the
transistors do not completely switch, and all devices are in the
active region during the oscillation period. On the contrary,
in the saturated-type VCO, the transistors completely switch,
resulting in a larger oscillation amplitude. It is well known
that the phase noise performance improves with the increase
in oscillation amplitude [3].
Another important requirement is the large tuning range of
more than 80% to cover the frequency band of 1–5.4 GHz for
multistandard applications. There are several different types of
delay line circuits reported in the literature, i.e., source-coupled
delay line, cross-coupled delay line, and inverter-based delay
line [4]. However, none of aforementioned is appropriate for
the large tuning range and good phase noise performance at
same time.
The circuit schematic of a VCDL, which is similar to the one
presented in [5], is shown in Fig. 2. These delay line simulations
show acceptable phase noise performance, a large bandwidth,
and a large tuning range at the same time. It consists of an
input n-type MOS pair (Mn1–Mn2) and a p-type MOS (PMOS)
positive feedback pair (Mp1–Mp2), which helps to maintain a
large oscillation amplitude at higher frequencies.
The VCO frequency can be tuned using a variable capacitor
(varactor) or a variable load. A varactor, which is typically
implemented by a p-n junction, limits the frequency tuning
range to 10%–20%. In this design, the frequency tuning is
obtained by tuning the conductance of the diode-connected
PMOS load (Mp3–Mp4). This conductance can be controlled
2871
Fig. 2. Circuit diagram of a basic VCDL.
by changing the bias voltage of PMOS transistor Mp5. The
delay line can be enabled or disabled by applying a control
signal (high or low) at the gate of transistor Mn3.
A simple analysis of the basic delay line shows that the
tuning range of an oscillator based on a VCDL is mainly
dependent upon the ratio of the transconductance of the input
pair Mn1–Mn2 and positive feedback pair Mp1–Mp2 [5].
1 gmn1
2πN CL
2
2
gmn1
− gmp1
1
≈
2
2πN
CL
⎛
⎞
2
gmp1
≈ fmax ⎝1 − 1 − 2 ⎠
gmn1
fmax ≈
fmin
frange
(1)
(2)
where N is the number of VCDL stages, and CL is the cumulative parasitic capacitance of gate, drain, or source of transistors
Mn1–Mn2, Mp1–Mp2, and Mp3–Mp4 attached to the output node.
The phase noise in a ring oscillator comes from three fundamental noise sources, which can be attributed to the transistor
white noise, flicker noise, and coupled noise from substrate,
control, and supply lines. The low-frequency flicker noise of
the differential input pair is not responsible for the phase
noise; rather, the flicker noise of tail transistors Mn3 and Mp5
modulates the VCO with random frequency modulation [6].
As the single-ended ring oscillators are extremely sensitive
to the supply noise, a differential structure is a natural choice.
Ideally, in differential structures, the supply noise appears in
common mode and is rejected by the next delay stage in
the chain. However, in practice, the direct parasitic coupling
between the supply line and the output cannot be eliminated,
and its effect becomes even worse at high frequencies.
The phase noise of a ring oscillator increases with the number
of stages for a given fixed frequency and power. This effect, as
verified by simulations, can be mitigated by keeping the total
phase noise almost constant at the expense of elevated power
consumption.
2872
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 11, NOVEMBER 2010
Fig. 3. Circuit diagram of a modified dual VCDL for a five- or ninestage VCO.
III. D ESIGN OF THE S TIMULUS G ENERATOR C IRCUIT
The maximum oscillation frequency of a VCO based on the
VCDL shown in Fig. 2 is proportional to gmn1 /CL . Since CL
is the sum of all parasitic capacitances at the output node, this
means that a large input transistor pair (Mn1–Mn2) and a small
load (Mp3–Mp4) and cross-coupled (Mp1–Mp2) transistor pair
will result in the highest oscillation frequency.
To maintain the oscillation of the VCO, the total phase shift
of the delay chain should be 360◦ with a unity gain. This implies
that the transconductance gmp1 should be large enough to
compensate the total load conductance gmp3 + gdsp3 + gdsp1 +
gdsn1 to maintain the desired phase shift, while the gain is more
than or equal to unity. To achieve the large tuning range, the
ratio of Mp1 and Mn1 transconductance (gmp1 /gmn1 ) should
be as large as possible but less than unity. From (2), it is obvious
that50% frequency tuning is achievable for a gmp1 /gmn1 ratio
of 3/4 (Fig. 2). The size of Mn1 is mainly determined by
the desired highest oscillation frequency. Intuitively, it seems
possible to increase the tuning range by increasing the size of
Mp1. Practically, when the size of Mp1 is increased
beyond
the size that maintains a gmp1 /gmn1 ratio equal to 3/4, the
VCO tuning range increases and then starts decreasing due to
the dominance of cumulative parasitic capacitance CL . Using
the iterative simulations, we were not able to achieve a tuning
range of more than 70% and a maximum frequency of 5.5 GHz
(at same time) for a five-stage VCO using the VCDL circuit
shown in Fig. 2.
To achieve the desired frequency tuning range of 80%, the
basic VCDL in Fig. 2 is modified into the dual VCDL shown
in Fig. 3. The dual VCDL provides the flexibility to design a
VCO that is seamlessly switchable between two configurations
with a different number of delay lines, providing the cumulative
tuning range of more than 80%. The additional differential
input pair (Mn4–Mn5) facilitates switching between nine- and
five-stage configurations (Fig. 4). The VFast and VSlow control
signals enable or disable the input differential pair of the dual
VCDL to work in either a nine-stage (slow-mode) or fivestage (fast-mode) configuration. All the transistors used in the
dual VCDL have a minimum length of 90 nm. The input
differential pairs (Mn1–Mn2 and Mn4–Mn5) and cross-coupled
pair (Mp1–Mp2) transistors have a size of 20 μm/0.09 μm each.
Only one input transistor pair is switched on at a time. The
load transistor pair size (Mp6–Mp7) is 40 μm/0.09 μm, which
is twice as large compared to the input pair. By varying the
voltage VCtrl , the oscillation frequency can be tuned anywhere
over the entire tuning span. An additional load pair (Mp6–Mp7)
consisting of very small transistors of 2 μm/0.09 μm is used,
which changes the frequency in fine steps of a few megahertz
by changing the analog control voltage VFine . This variation
is around the oscillation frequency set by the control voltage VCtrl .
The simulation shows that the nine-stage VCO (slow mode)
covers the frequency range of 0.88−2.71 GHz (67.5%),
while the five-stage VCO (fast mode) covers 2.49−5.63 GHz
(55.7%). Collectively, the stimulus generator can produce a
two-tone stimulus with a tone spacing of 3 MHz to 4.75 GHz.
The VCO output signal is buffered using a seven-stage differential tapered buffer to avoid loading and to maintain a high
degree of isolation between the two VCOs.
An adder circuit is used to add these signals generated by
separate VCOs to perform a two-tone test. In terms of linearity,
this circuit should be superior to the front end under test,
particularly for input-third-intercept-point (IIP3) testing. In our
design, the adder has two functions: addition of two signals and
power control with a large dynamic range. There is a tradeoff
between the dynamic range and linearity of the adder circuit. To
break this tradeoff, we can split the adder with power control
into two stages: highly linear adders with no power control
followed by an inherently linear passive attenuator for power
control. This scheme needs a relatively large silicon area and a
higher number of pins for test and control signals. Therefore,
we resorted to a simple circuit that can provide both addition
and power control in one stage with a small area and a lower
pin count, as shown in Fig. 5.
The single- or two-tone differential test signals are ac coupled (using C1 and C2) to the input of a wideband inductorless
LNA through switches S1 and S2. The LNA and switches
are codesigned to account for their parasitic capacitances.
Simulations show that the wideband inductorless LNA used
in this design is quite insensitive to the parasitic capacitances
introduced by switches S1 and S2. Moreover, the switch size
is only 20 μm/90 nm compared to the size of the LNA input
transistor, which is 150 μm/90 nm. Therefore, the difference in
the on/off parasitic capacitance of switches S1 and S2 does not
have any measurable effect on front-end performance.
IV. M EASUREMENT R ESULTS
A test chip containing wideband RF front end and stimulus generator circuitry was manufactured in 90-nm CMOS
[10]. The two VCOs are placed apart on the 1 × 1 mm2 chip
with a separate power supply to minimize the supply and
RAMZAN et al.: ON-CHIP STIMULUS GENERATOR FOR GAIN, LINEARITY, AND BLOCKING PROFILE TEST
Fig. 4.
Block diagram of a switchable five-/nine-stage wide-tuning VCO.
Fig. 5.
Circuit diagram of variable output adder with 50-Ω drive capability.
2873
Fig. 7. VCO tuning characteristic versus VCntrl in slow and fast modes.
Fig. 8. VCO tuning characteristic versus VFine for different oscillation
frequencies.
Fig. 6. Macrograph of a wideband RF front end with the on-chip stimulus
generator.
substrate coupling (see the micrograph in Fig. 6). To avoid
injection locking, the oscillator outputs are heavily buffered,
and power supplies are carefully decoupled using large parasitic
gate capacitances of the transistors, which are particularly laid
out for this purpose. During measurement, any symptoms of
injection locking are not observed for a tone spacing as small as
3 MHz. A tone spacing of less than 3 MHz cannot clearly be
distinguished due to the phase noise of the VCOs.
A VCO in its slow mode, which is composed of nine VCDLs,
achieves a tuning range of 65% (0.923−2.65 GHz). In the fast
mode, the tuning range is 55% (2.52−5.61 GHz). Collectively,
this covers the frequency band of interest (1−5.4 GHz) with
a cumulative tuning range of 83.6%, as plotted in Fig. 7. As
shown in Fig. 8, the control signal VFine brings variations
2874
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 11, NOVEMBER 2010
Fig. 9. Measured phase noise plot at 5.4 GHz.
Fig. 11.
Single-tone VCO power at adder output versus adder bias current.
Fig. 12.
VCO power consumption versus frequency.
Fig. 10. Phase noise of the test circuit at different oscillation frequencies.
(Δfrequency) in frequency mainly determined by signal VCtrl .
VFine is used to adjust the VCO frequency in very small steps of
a few megahertz, enabling us to generate two stable tones with
a small frequency spacing.
The phase noise performance of the VCO at 5.5 GHz is
shown in Fig. 9. At the offset frequency of 10 MHz, a phase
noise of −85 dBc/Hz is measured. The VCO phase noise performance degrades at higher oscillation frequencies, as shown
in Fig. 10. The use of a phase-locked loop (PLL) can improve
the phase noise performance of the VCO, but designing a PLL
with such a large bandwidth is an extremely challenging task.
The output power of the test signal can be controlled using the
bias currents (Ibias1 and Ibias2 ) of the adder circuit. The plot
in Fig. 11 shows that the output power of a single tone can be
controlled from −36 to −3 dBm at 1 GHz. This dynamic range
of the VCO drops by approximately 4 dB as the oscillation
frequency increases from 1 to 5.5 GHz. For two tones, the
dynamic range further reduces by approximately 3 dB. The
power consumption of a single VCO including the adder circuit
for an output power of −10 dBm is plotted in Fig. 12. The
power consumption increases with the frequency for both slow
and fast modes. Since the test circuit is operational only during
the test mode, higher power consumption is acceptable.
V. W IDEBAND F RONT-E ND M EASURMENTS
The gain, 1-dB CP, and blocking profile of a wideband front
end consisting of an LNA and a mixer are measured using
Fig. 13. Error in gain and 1-dB CP measured using the on-chip stimulus
generator compared to the actual values versus local oscillator (LO) frequency.
the on-chip stimulus generator. The stimulus is measured by a
spectrum analyzer. The difference between the measured values
and the actual values measured by standard RF instrumentation is plotted in Fig. 13. The maximum gain error is within
±8%, while the maximum error in the 1-dB CP is within
±10%. In production testing, the on-chip power detector can
be used to measure power of the input and output signals
[1]. The major challenge is to reduce or mitigate the effect of
process variation on these simple on-chip detectors designed in
nanometer CMOS technologies. There are techniques reported
RAMZAN et al.: ON-CHIP STIMULUS GENERATOR FOR GAIN, LINEARITY, AND BLOCKING PROFILE TEST
2875
TABLE I
P ERFORMANCE C OMPARISON W ITH R ECENT P UBLICATIONS
Fig. 14. Comparison of blocker profiles of the front end using the on-chip
stimulus generator and standard equipment.
VI. S UMMARY AND C ONCLUSION
Fig. 15. Percentage error in the blocker profile of the front end using the onchip stimulus generator and standard equipment.
in the recent literature particularly focusing on the calibration
of on-chip RF detectors [11].
The main advantage of the presented stimulus generator is
the availability of two tones on a chip. These tones can be
generated with an arbitrary frequency spacing (from a few
megahertz to gigahertz) and independent power control, specifically when the low power tone mimics an in-band desired signal
and the high power tone imitates an out-of-band blocker. The
measured and actual blocking profiles are plotted in Fig. 14.
The maximum error between these two plots is within ±18%,
as shown in Fig. 15.
The main source of the error in measurement is the fluctuation in the amplitude of the oscillator output signal. These amplitude variations originate from different sources like FM–AM
noise folding or ripples present in the supply lines. These
errors can be further reduced by using on-chip power supply
regulators and a better decoupling scheme.
The third intercept point (IP3) is another measure of nonlinearity in addition to the 1-dB CP. This circuit metric can only
be measured reliably when the IP3 of the stimulus generator
is better than the IP3 of the circuit under test. In our case, the
output IP3 of the adder circuit is −8 dBm, while the front-end
IIP3 is close to 0 dBm, so the IP3 measurement is not feasible.
However, it is possible to design a highly linear adder circuit to
achieve this goal compared to the simple adder circuit used in
this design at the expense of an increase in area overhead.
In this paper, a differential stimulus generation circuitry
consisting of two VCOs and an adder with 50-Ω drive capability
has been presented. The summary of the VCO performance
and comparison with the published CMOS VCOs with wide
and continuous tuning range has been provided in Table I. Our
modified dual-VCDL-based VCO has a wide tuning range of
83.6%, close to 50% duty cycle, and low phase noise, and it
occupies an area of 0.012 mm2 .
The VCO presented in [9] has the tuning range of 90%,
but the used delay cell architecture and three-stage architecture
cannot easily be modified to have an additional control to
change the frequency in small steps of a few megahertz.
The proposed stimulus generator can generate a single- or
two-tone stimulus with a dynamic range of more than 30 dB
and occupies the total area of 0.03 mm2 including the coupling
capacitors.
This stimulus generation circuitry has been successfully used
to test the gain, 1-dB CP, and blocking profile of a front
end with an error of ±8%, ±10%, and ±18%, respectively.
In volume production, the pass/fail tolerance limits are very
carefully chosen. If the pass/fail limits are stringent, yield loss
will increase. Contrary to this, the defective parts per million
(DPPM) will increase if the tolerance limits are too relaxed.
Therefore, the best values of pass/fail tolerances are calculated
based on the optimal compromise between DPPM, yield loss,
and test time [12]. Keeping in mind the current industrial
practices, the magnitude of the measured errors seems plausible
for screening out faulty chips in volume production.
R EFERENCES
[1] R. Ramzan, S. Andersson, J. Dabrowski, and C. Svensson, “Multiband RF-sampling receiver front-end with on-chip testability in 0.13 μm
CMOS,” Analog Integr. Circuits Signal Process., vol. 61, no. 2, pp. 115–
127, Nov. 2009, DOI: 10.1007/s10470-009-9286-x.
[2] L. Dai and R. Harjani, “Design of low-phase-noise CMOS ringoscillators,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,
vol. 49, no. 5, pp. 328–338, May 2002.
[3] C. H. Park and B. Kim, “A low-noise, 900-MHz VCO in 0.6- μm CMOS,”
IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 586–591, May 1999.
[4] D. A. Badillo and S. Kiaei, “Comparison of contemporary CMOS ring
oscillators,” in Proc. RFIC Symp., Jun. 2004, pp. 281–284.
2876
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 11, NOVEMBER 2010
[5] W. Yan and H. Luong, “A 900-MHz CMOS low-phase-noise voltagecontrolled ring oscillator,” IEEE Trans. Circuits Syst. II, Analog Digit.
Signal Process., vol. 48, no. 2, pp. 216–221, Feb. 2001.
[6] A. A. Abidi, “Phase noise and jitter in CMOS ring oscillators,” IEEE J.
Solid-State Circuits, vol. 41, no. 8, pp. 1803–1816, Aug. 2006.
[7] T. Tong, Z. Wenhua, J. M. Hvolgaard, and T. Larsen, “0.18 μm CMOS
low power ring VCO with 1 GHz tuning range for 3–5 GHz FM-UWB
applications,” in Proc. IEEE ICCS, 2006, pp. 1–5.
[8] R. Tao and M. Berroth, “The design of 5 GHz voltage controlled ring
oscillator using source capacitively coupled current amplifier,” in Proc.
RFIC Symp., 2003, pp. 623–626.
[9] A. Georgiadis and M. Detratti, “A linear, low-power, wideband CMOS
VCO for FM-UWB applications,” Microw. Opt. Technol. Lett., vol. 50,
no. 7, pp. 1955–1958, Jul. 2008.
[10] R. Ramzan, “A 0.5–6 GHz low gain RF front-end for low-IF oversampling receivers in 90 nm CMOS,” Ph.D. dissertation, No. 1261,
Linköping Univ., Linköping, Sweden. ISBN 978-91-7393-601-9.
[11] R. Ramzan and J. Dabrowski, “On-chip calibration of RF detectors by DC
stimuli,” in Proc. RFIC Symp., 2008, pp. 571–574.
[12] O. Eliezer and I. Bashir, “Digital hardware and software based mechanisms for calibration and compensation in wireless SoCs,” in Proc. RFIC
Symp. Workshop (WSL), 2008, pp. 1–30.
Naveed Ahsan (M’09) received the B.E. degree
from University of Engineering and Technology,
Lahore, Pakistan, in 1998, the M.S. degree from
the National University of Sciences and Technology
(NUST), Rawalpindi, Pakistan, in 2002, and the
Ph.D. degree from Linkoping University, Linkoping,
Sweden, in 2009.
After graduation, he joined the Advanced Engineering Research Organization, Islamabad, Pakistan,
where he worked on low-profile microstrip antennas
and RF system design. His research interests are
mainly focused on flexible RF front-end design.
Rashad Ramzan (M’09) received the B.E. degree
with honors from University of Engineering and
Technology, Lahore, Pakistan, in 1994, the M.S. degree from the Royal Institute of Technology (KTH),
Stockholm, Sweden, in 2003, and the Ph.D. degree on testable and reconfigurable RF circuits from
Linkoping University, Linkoping, Sweden, in 2009.
He worked on mixed signal system design and
VLSI deign for eight years in different companies
in Pakistan and abroad. He is currently with the
Department of Electrical Engineering, National University of Computer and Emerging Sciences, Islamabad, Pakistan. His research
interests are mainly focused on fully integrated transceivers and design for
testability.
Jerzy Dabrowski (M’03) received the Ph.D. and
D.S. degrees form the Silesian University of Technology, Gliwice, Poland.
He has specialized in macromodeling and simulation of analog and mixed-signal circuits. Currently,
he is an Associate Professor with the Electrical
Engineering Department, Linkoping University,
Linkoping, Sweden. He is the author of more than 80
published research papers in international journals
and conference proceedings and one monograph.
He is the holder of 12 patents (as a coauthor) in
switched-mode power supplies and electronic instrumentation. His recent research interests are in RF IC design and design for testability for analog/RF
circuits.