Download TESTING READINESS REVIEW T I R

TELEMETRIC INTERPLANETARY REGOLITH EXPLORER FOR SEISMIC
INVESTIGATION OF ASTEROID SURFACES
TESTING READINESS REVIEW
Aerospace Engineering Sciences
University of Colorado
3 March 2014
Ian Barry
Rachael Collins
Jonathon Fraker
Patrick Haas
Tom Johnson
Austin Lillard
John Marcantonio
Scott Taylor
OUTLINE

Overview

Schedule

Testing Readiness


Communications System

Power System

Mechanical System
Budget
2
OVERVIEW
PROJECT CONOPS



1.5 ft
Transmitter
3lb weight
Power

Receiver
C&DH Board
ADC

Thermistors
w/MUX
Internal
GeoPod
Structure
Heaters
During
this
time,
the
power
The
Board
continues
3-axis
accelerometer
Weight
dropped
near
fully
ADC
C&DH
converts
board
samples
6multiplexed
analog
and
internal
structure
must
GeoPod
detects
seismic
DataC&DH
from
the
Commands
Packetized
accelerometer
are
received
system
must
regulate
to
sample
both
the
measures
response
integrated
GeoPod
channels
stores
the
(2
digital
signals
data
for
from
each
integrate
the
components
waves
thermistors
(“housekeeping
over
and
thermistor
the
next
20data
minutes
isand
to
distribute
power
toat
all
of
accelerometer
data
and
the
the
ADC
at
500Hz
axis)
into
athe
and
the
system
into
data”)
ispower
sampled
500Hz
start
transmitted
transmissions
according
of
data
to
BASIX
mission
will
use
both
components
thermistors
for
15an
minutes
digital
signal.
the
GeoPod
shell
(provided
and
stored
at
80
bits/s
received
commands
a
GeoPhone
and
20
minutes
represents
a
by
Ball) window
Heaters
are not necessary
Accelerometer
contact
for
Ourground
projecttesting.
will sample each
Representative
loads will be
axis of the accelerometer
used
simulation
twice for
to simulate
the
GeoPhone, because
commercial GeoPhones are
too large, heavy, and
expensive for our project
 Ball is receiving a
custom GeoPhone
Accelerometer
1 ft
Overview
Schedule
Testing Readiness
Budget
4
DESIGN OVERVIEW
ADC Board
Power Board
Arduino Due
Receiver
Transmitter
Battery Pack
Overview
Schedule
Testing Readiness
Budget
5
FUNCTIONAL BLOCK DIAGRAM
6
ELECTRONICS BLOCK DIAGRAM
Overview
Schedule
Testing Readiness
Budget
7
CRITICAL PROJECT ELEMENTS
Element
Name
Description
MSN.1
Mass
Total mass of geopod shall be less than 5 kg
MSN.2
External Shell
Integration
All subsystems shall be integrated into existing 3000 mL
spherical external shell
MSN.3
Data
Collection
The GeoPod shall collect and store accelerometer and
housekeeping data
MSN.4
Transmission
The GeoPod shall be capable of transmitting all collected
data to the Ground Station Equipment (GSE) within the
mission duration
MSN.5
Thermal
Range
The GeoPod shall be kept within the operating
temperature range of GeoPod components
MSN.6
Power
The GeoPod shall be able to power itself for the mission
duration
MSN.7
Path to Flight
The designed subsystems shall have no critical
obstacles in their development toward a space-qualified
system
Overview
Schedule
Testing Readiness
Budget
8
SCHEDULE
WORK BREAKDOWN STRUCTURE
TIRESIAS
Project
Management
• CDR
• FFR
• Work Flow
Schedule
• Cost Budget
• MSR
• AIAA Paper
• PFR
• SFR
Overview
Comm System
• Link Budget
• Transmitter
and Receiver
• Antennas
• Accelerometer
• Configured
ADC
• C&DH SW
Sketches
• Stored Data
• Spacecraft
Simulation
(GSE)
Schedule
Mechanical
System
Power System
• Power Budget
• Schematics
• Power
Distribution
PCB
• ADC PCB
• Temperature
Sensors
• Wiring Harness
• CAD Models
• Thermal Model
• Mass and
Volume Budget
• Battery Pack
• Shell
Integration
Structure
• Subsystem
Mounting
Frame
Testing Readiness
Budget
Integration and
Test
• TRR
• Safety
Protocols
• Interface
Control
Documents
• As Run
Procedures
• Results
Documents
• Integrated
GeoPod
10
COMMUNICATIONS SCHEDULE
Overview
Schedule
Testing Readiness
Budget
11
POWER SCHEDULE
Overview
Schedule
Testing Readiness
Budget
12
MECHANICAL SCHEDULE
Overview
Schedule
Testing Readiness
Budget
13
TESTING SCHEDULE
Overview
Schedule
Testing Readiness
Budget
14
TESTING READINESS
COMMUNICATIONS SYSTEM
COMM REQUIREMENTS
Rotational
Period = 2.4hrs
freq < 50 Hz
Max. Amplitude:
0.2 g’s
Asteroid
Orbital
Period =
124.1hrs
60o
Requirement Flows From
Description
COM.1
MSN.3
6 channels of science data shall be sampled at 500 Hz.
COM.2
MSN.3
Science data shall be recorded such that a range of -2g to
2g is quantized with a resolution of 0.002g
COM.3
MSN.3,
MSN.4
The C&DH board shall interface with ADC, memory, power
board, and RF system.
COM.4
MSN.4
Uplink data rate shall ensure all stored telemetry is
transmitted during the 20 min contacts over 10 days
Overview
Schedule
Testing Readiness
Budget
17
DATA COLLECTION TEST

Goal: Measure data collection rate (COM.1) and
characterize signal conditioning output (COM.2)
Measure ADC conversion frequency,
Verify sampling rate
SPI Logic
Analyzer
Measure SNR and bias of data,
Verify signal conditioning output
CCSC
Verified
Dual (20/5V)
Power Supply
Signal
Generator
Timing
Verified
MUX
Redesign
Pending
Measure data stored,
Verify recording rate
9V Power
Supply
Overview
Schedule
Testing Readiness
Budget
18
DATA COLLECTION MODELS
Signal Conditioning (COM.2)

New design of CCSC (decoupling
capacitor, idle current bias)
Software Timing (COM.1)





Overview
Schedule
New Dataflash card
 Smaller page size (4x)
 Faster SPI clock speed (86
MHz)
Required duration < 2 ms
Predicted duration = 1.126 ms
Tested duration = 1.121 ms
500 Hz met within 0.0021%
Testing Readiness
Budget
19
TELEMETRY PLAYBACK TEST

Goal: Measure effective data transmission rate (COM.4) and identify bit errors

Verify ability to transmit 3.6 MB of data in 20 min. and receive commands to transmit
Pre-integration Measure data transmitted,

Verify 32 kbps transmission rate
GSE
Antenna
Bytes
Sent
Receiver
9V Power
Supply
Measure delay between command
and packet receipt,
Verify response to command
Test RX
Arduino
Stand
Hard line to
command
MATLAB Processing
Memory
Read
Overview
Schedule
Send error packets,
Verify bit error identification
Testing Readiness
Budget
Checksums
Calculated
20
TELEM. PLAYBACK MODELS
Link Budget
BER Packet Error


8-bit modular checksum used to
detect all single-bit errors
88% of two-bit errors detected: 1
occurrence expected in 15,030 total
packets
Packet Error Prediction
Packet Size
BER
Packets Played-back
Packet Error Probability
Expected Retrans Packets
Overview
8328 bits
10-6
15,030
0.8%
125
Schedule



75 dB margin calculated with 10-6 BER at
32 kbps using antennas (15 dB in space
with 10 km range)
Single bytes successfully transmitted over
antennas w/ 21 dB of attenuation
4-20 dB VSWR return loss measured
Data Parameters
Bit Error Rate
Data Rate
Range
Link Budget:
Transmitter Power
EIRP
Propagation Losses
Antenna Gain (Both Ends)
Received Power
System Noise Power
Carrier to Noise Ratio Density
Minimum Pr/No
Link Margin
Testing Readiness
Budget
10-6
32,000
10
[-]
bps (Hz)
m
20
-27.08
-46.01
5.11
-68.0
-200.47
132.50
57.75
74.75
mW
dBW
dB
dB
dBW
dBW-Hz
dB-Hz
dB-Hz
dB
21
POWER SYSTEM
POWER REQUIREMENTS
Critical Components
 Batteries
 Capacity and size
 Power Regulation and Distribution
 Efficiency and accuracy
Requirement Flows From
Description
EPS.1
MSN.3,
MSN.4
The power system shall output voltage lines at 5, 9.5, 20,
and 12 volts
EPS.2
MSN.5
The batteries shall supply power for 12 days of operations
EPS.3
MSN.1
Power Distribution board shall fit on 4.25x4.25 in. PCB
EPS.4
EPS.1,
EPS.2
The Power Distribution board must be >90% efficient
Overview
Schedule
Testing Readiness
Budget
23
POWER VERIFICATION
Goal: Measure regulation accuracy (EPS.1) and power board efficiency (EPS.4)
110-mΩ current
sense resistors
33-Ω
Load
12V
Supply
Acceptance to Date

25-mΩ current
sense resistors
200-Ω
Load
27V
Supply
25-Ω current
sense resistors
Overview
Battery capacity
measured to 530 ± 20 Wh at peak load (spec: 500
W-h)
Measure Current and Voltage,
Verify accuracy and efficiency
10-kΩ
Load
Schedule
Testing Readiness
Budget
24
REGULATION MODELS
Voltage Lines (EPS.1)
 Regulator outputs measured to find
limiting input voltages
 5V regulator output = 5.3 V from
resistor inaccuracy
 Required: 5.25 V
 9.5V and 20V lines within bounds
90% Efficiency (EPS.4)

Model

Overview
Schedule
Current
Draw
Voltage
Drop
Power
Loss Efficiency
5V LDO
26 mA
4.5 V
118 mW
53%
9.5V SR
265 mA
2.5 V
115 mW
96%
20V LDO
2 mA
7V
14 mW
74%
Board Total
237 mW
91%
Results
Current
Draw
Voltage
Drop
5V LDO
27 mA
4.5 V
117 mW
55%
9.5V SR
259 mA
2.5 V
88 mW
97%
20V LDO
3 mA
7V
44 mW
50%
Board Total
248 mW
93%
Testing Readiness
Budget
Power
Loss Efficiency
25
MECHANICAL SYSTEM
MECHANICAL REQUIREMENTS
Requirement Flows From
Description
MCH.1
MSN.2
The internal structure shall integrate with the
manufactured GeoPod shell
MCH.2
MSN.2
The power and electrical subsystems shall be accessible
for extraction without the removal of other components
MCH.3
MSN.5
A thermal model shall be created to ensure subsystems are
within operating temperatures in the testing environment
MCH.4
MSN.7
All internal structural components shall be manufacturable
using on campus resources
Overview
Schedule
Testing Readiness
Budget
27
MASS BUDGET
Mass Budget
 Actual Margin of 1.23 kg or 24 %
 Increase due to addition of wiring
Overview
Schedule
Comm System
Power System
Mechanical
System
Budget
28
SUBSYSTEM INTEGRATION TEST
ADC Board
Arduino Due
Requirements Satisfied
MCH.1
MCH.2
MCH.4
Receiver
Remaining Integration
Battery Pack
Wiring
Power Board
Transmitter
Overview
Schedule
Testing Readiness
Budget
29
THERMAL VERIFICATION MODEL
Thermal Operating Range (MCH.3)
Cold Case:
Internal Structure Material:
Aluminum 6061
Op.
Range
[°C]
Temp at
Steady
State
[°C]
Arduino
Due/ADC
Cold: -40
Hot: 85
Cold: 21.47
Hot: 23.88
+0.47
+2.88
Power Board
Cold: -40
Hot: 140
Cold: 21.46
Hot: 23.85
+0.46
+2.85
Battery Pack
Cold: -20
Hot: 55
Cold: 21.55
Hot: 23.97
+0.55
+2.97
Transmitter/
Receiver
Cold: -20
Hot: 50
Cold: 21.50
Hot: 23.93
+0.50
+2.93
Subsystem
Hot Case:
Overview
Schedule
Testing Readiness
Budget
Temp
Change
[°C]
30
THERMAL VERIFICATION
V
115 VAC
Wall Outlet
Variac
70W Heater
Obtained, Not
Yet Tested
Structure FitChecked and
Integrated
Goal: Isolate and measure modeled
thermal conductive resistances (MCH.3)
 Resistances independent of
thermal loads, symmetric within
bounds
 Resolution of 1.7 K/W

Various levels of integration with and
without batteries
Measure steady-state temperatures over
representative orthant of pod
Verify modeled thermal resistances
Stefaan
Van Wal’s
Gravel Box
3 Surface
Thermocouples
Available, Not
Yet Set Up
NI 9213 DAQ
5 Interior
Thermocouples
Overview
LabView VI
Tested, Not Yet
Calibrated
Schedule
Testing Readiness
Budget
31
GEOPOD SYSTEM
SYSTEM VALIDATION
Benchtop Test

Fully Integrated Validation
Power Board Verification
 Electrically integrated
 Batteries
 Accuracy and efficiency
with real loads
Command Cable



Antenna
Thermocouple Wires

Accelerometer
Data Collection
 Representative stimulus in
gravel
Telemetry Playback
 Full comm. path, short range
Integrated Thermal Model Validation
 Temperature rises correlated to
predicted mission heat loads
Battery-powered, wires for
thermocouples and commands only
3 lb. weight
1 ft.
Stefaan
Van Wal’s
Gravel Box
33
BUDGET
PROCUREMENT STATUS
Financial Plan
Part
Cost
Breakout Boards and Prototyping
Arduino’s (Cables and Board)
$161
$176
Mechanical Supplies
$397
Batteries
PCBs
$230
$334
Headers and Cables
$47
Electrical Components (ICs/Res/Caps/Cables)
$331
Transmitter and Receiver
Total
Budget
Current Budget
Overview
Schedule
Testing Readiness
$1,831
$3,506
$5,000
$1,494
Budget
35
COST PLAN
Financial Plan
Part
Cost
Contingency
Total
IC’s
Resistor, Capacitors, Inductors, Diodes
Cables/Adapters
$66
$20
$20
$39
100%
100%
30%
30%
$132
$40
$26
$50
Batteries
$20
20%
$24
Testing Equipment
$10
30%
Total
Budget Left
Final
Margin
$13
$285
$1,494
$1,208
24%
PCBs
Overview
Schedule
Testing Readiness
Budget
36
ACKNOWLEDGMENTS
Customer – Ball Aerospace

Joseph Hackel
Course Coordinator

Dr. Dale Lawrence
Faculty Advisor

Dr. Scott Palo
Principal Investigator

Dr. Daniel Scheeres
37
QUESTIONS?
APPENDIX
DATA STORAGE
Data formatted and stored into packets based on CCSDS standard
Original designed packet size was 8328 bits
New packet format is 1992 bits:



8
16
4
2
34
1920
8
Syn
c
Frame ID
Probe ID
VCID
Timestamp
Telemetry
Checksum
0
Pros



Cons
Packet size is one page in memory
Eliminates unnecessary complexity in
data collection software
BER of 1e-6 is not seen (no retrans)

8328
More overhead (commands) when
playing back telemetry
 Mitigated by CLTU blocks of
commands
Memory
Amount
Science
HK
20 min
15 min
Data Rate
24 kbps
64 bps
Total:
Margin:
Packets
Packets
(8328 bits) (1992 bits)
28.8 Mb
3488.4
15,000
0.058 Mb
6.97
30
29 Mb
3496
15,030
53%
Storage
40
ANTENNA CHARACTERISTICS
Voltage Standing Wave Ratio (VSWR)




Ball antenna tuned to 437.5 MHz
Freq. (MHz)
2 transmission frequencies available
to TIRESIAS
GS Antenna
 Licensed (Palo):
437.35 MHz
437.50 (Ball)
 ISM Band:
434.79 MHz
437.35 (Palo)
437.35 (Palo)
 Acceptable VSWR
434.79 (ISM)
 VSWR could be acceptable
 Decreased performance likely
VSWR
Return Loss
(dB)
1.19
21.0
1.19
21.2
2.91
6.3
437.50 (Ball)
1.75
11.3
437.35 (Palo)
1.65
12.2
434.79 (ISM)
3.57
5.0
434.79 (ISM)
S/C Antenna
Operational: VSWR < 2
Maximum: VSWR < 20
41
SIGNAL CONDITIONING CHANGE
Accel
9V
-5 to 5V
3-17V
-5 to 5V 5V
1.5-8.5V
3.3V
20V
CCSC



VD
LP
Removed Voltage Divider (No need to step
down voltage to be within ADC range)
Removed OpAmp (No negative supply rails)
Utilize ADCs high 1MΩ input impedance and 5 to 5V range
 Lower resolution of 0.0015g from
0.00052g, but still meets 0.002g
requirement
ADC
42
BODE – SIGNAL CONDITIONING

ADC was not powered on
43
BATTERY DISCHARGE SETUP
8 x 1.5
V AA
cells,
10-14 V
248.3 Ω
(2 x 100 Ω,
1 x 50 Ω)
Voltage
Probe
Point
BATTERY DISCHARGE RESULTS
Direct Sunlight
Heats Up Batteries
Conservative Capacity:
530 ± 20 Wh
Required Capacity:
248 Wh
DISCHARGE INTEGRATION
VOLTAGE ACCURACY TEST
Req EPS.1: Voltage Lines
 Voltage lines measured over a variety of input voltage ranges to determine
limiting values
 5V regulator tied to voltage of 9.5V regulator: Output = 5.3 V
 Outside bounds by 0.05 V due to inaccuracies in resistors
47
POWER REQUIREMENTS
Regulator
Type
Targeted
Voltage
Min. V
Max. V
Limiting Component(s)
5
4.75
5.25
ADC Power
Switching
9.5
9.0
10
Transmitter (Low Limit),
Arduino Power (High Limit)
LDO
20
18
22
Accelerometer Power
LDO
48
CHANGES TO POWER DESIGN
Related Req. Reason For Change
What changed
Changes from MSR
NewDesign
at MSROriginally
using
MOSFET
transistors
as switches
method
EPS.2
Found
that original
MOSFET
New IC electronic switches
of switching (Supply
transistors could not be
used to turn on/off
components power for
used for our project
components
mission
duration)
Old: STH310N10F7 – Power MOSFET
New: FDC6324 – Integrated Load Switch
49
POWER BOARD
Req. EPS.4: Power board size
50
TEST BED
51