Download lecture1

Lecture 1:
Introduction
Original Lecture notes ©
2010 David Money Harris
Modified by Konstantinos
Tatas
ACOE419 – Digital IC and VLSI Design
 ECTS: 5
 Conduct hours per week: 3 (2 Lecture – 1 Lab)
 Evaluation:
– Final Exam: 60%
– Laboratory exercises: 20%
– Test: 10%
– Assignment: 10%
1: Introduction
ACOE419 – Digital IC and VLSI Design
2
Course outline and
breakdown
 Week 1:
– Introduction to VLSI Design
 Week 2:
– Stick diagrams and layout
– Lab 1: Basic schematic entry
 Week 3:
– The ideal MOS transistor
– Lab 2: Compound gates
 Week 4:
– The non-ideal MOS transistor
– Lab3: Basic Layout
1: Introduction
ACOE419 – Digital IC and VLSI Design
3
Course outline and
breakdown
 Week 5:
– Logical Effort
– Lab 4: Advanced Layout
 Week 6:
– Power Consumption
– Lab 5: MOS transistor characteristics
 Week 7:
– Test
– Lab 6: Logical Effort
 Week 8:
– Simulation
– Lab 7: Power Consumption
1: Introduction
ACOE419 – Digital IC and VLSI Design
4
Course outline and
breakdown
 Week 9:
– Combinational Circuit Design
– Lab 8: Power Consumption
 Week 10:
– Wires
– Lab 9: Combinational Circuit Design
 Week 11:
– Sequential Circuit Design
– Lab 10
 Week 12:
– Adder Design
– Lab 11
1: Introduction
ACOE419 – Digital IC and VLSI Design
5
Introduction
 Integrated circuits: many transistors on one chip.
 Very Large Scale Integration (VLSI): bucketloads!
 Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors
 Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
 Rest of the course: How to build a good CMOS chip
1: Introduction
ACOE419 – Digital IC and VLSI Design
6
A Brief History
 1958: First integrated circuit
– Flip-flop using two transistors
– Built by Jack Kilby at Texas
Instruments
 2010
– Intel Core i7 mprocessor
• 2.3 billion transistors
– 64 Gb Flash memory
• > 16 billion transistors
Courtesy Texas Instruments
[Trinh09]
© 2009 IEEE.
1: Introduction
ACOE419 – Digital IC and VLSI Design
7
Growth Rate
 53% compound annual growth rate over 50 years
– No other technology has grown so fast so long
 Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society
[Moore65]
Electronics Magazine
1: Introduction
ACOE419 – Digital IC and VLSI Design
8
Annual Sales
 >1019 transistors manufactured in 2008
– 1 billion for every human on the planet
1: Introduction
ACOE419 – Digital IC and VLSI Design
9
Invention of the Transistor
 Vacuum tubes ruled in first half of 20th century Large,
expensive, power-hungry, unreliable
 1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs
– See Crystal Fire
by Riordan, Hoddeson
AT&T Archives.
Reprinted with
permission.
1: Introduction
ACOE419 – Digital IC and VLSI Design
10
Transistor Types
 Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
 Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration
1: Introduction
ACOE419 – Digital IC and VLSI Design
11
MOS Integrated Circuits
 1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle
[Vadasz69]
© 1969 IEEE.
Intel
Museum.
Reprinted
with
permission.
Intel 1101 256-bit SRAM
Intel 4004 4-bit mProc
 1980s-present: CMOS processes for low idle power
1: Introduction
ACOE419 – Digital IC and VLSI Design
12
Moore’s Law: Then
 1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months
Integration Levels
SSI:
10 gates
MSI: 1000 gates
LSI:
[Moore65]
10,000 gates
VLSI: > 10k gates
Electronics Magazine
1: Introduction
ACOE419 – Digital IC and VLSI Design
13
And Now…
1: Introduction
ACOE419 – Digital IC and VLSI Design
14
Feature Size
 Minimum feature size shrinking 30% every 2-3 years
1: Introduction
ACOE419 – Digital IC and VLSI Design
15
Corollaries
 Many other factors grow exponentially
– Ex: clock frequency, processor performance
1: Introduction
ACOE419 – Digital IC and VLSI Design
16
Silicon Lattice
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors
1: Introduction
Si
Si
Si
Si
Si
Si
Si
Si
Si
ACOE419 – Digital IC and VLSI Design
17
Dopants





Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
1: Introduction
Si
Si
Si
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
Si
-
+
+
-
Si
Si
Si
ACOE419 – Digital IC and VLSI Design
18
p-n Junctions
 A junction between p-type and n-type semiconductor
forms a diode.
 Current flows only in one direction
1: Introduction
p-type
n-type
anode
cathode
ACOE419 – Digital IC and VLSI Design
19
nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor
Source
Gate
Drain
Polysilicon
– Even though gate is
SiO2
no longer made of metal
n+
Body
p
1: Introduction
ACOE419 – Digital IC and VLSI Design
n+
bulk Si
20
nMOS Operation
 Body is usually tied to ground (0 V)
 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
0
n+
n+
S
p
1: Introduction
D
bulk Si
ACOE419 – Digital IC and VLSI Design
21
nMOS Operation Cont.
 When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source
Gate
Drain
Polysilicon
SiO2
1
n+
n+
S
p
1: Introduction
D
bulk Si
ACOE419 – Digital IC and VLSI Design
22
pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
1: Introduction
bulk Si
ACOE419 – Digital IC and VLSI Design
23
Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
1: Introduction
ACOE419 – Digital IC and VLSI Design
24
Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to drain
d
nMOS
pMOS
g=1
d
d
OFF
g
ON
s
s
s
d
d
d
g
OFF
ON
s
1: Introduction
g=0
s
ACOE419 – Digital IC and VLSI Design
s
25
CMOS Inverter
A
Y
0
1
1
0
VDD
A
0
1
OFF
ON
Y
ON
OFF
A
Y
GND
1: Introduction
ACOE419 – Digital IC and VLSI Design
26
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
ON
OFF
OFF
ON
A
B
1: Introduction
1
0
0
1
1
0
ACOE419 – Digital IC and VLSI Design
OFF
ON
Y
ON
OFF
OFF
ON
ON
OFF
27
CMOS NOR Gate
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
1: Introduction
A
B
Y
ACOE419 – Digital IC and VLSI Design
28
3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0
Y
A
B
C
1: Introduction
ACOE419 – Digital IC and VLSI Design
29
Example
 Sketch a 3-input CMOS NOR gate
1: Introduction
ACOE419 – Digital IC and VLSI Design
30
Complementary CMOS
 Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
inputs
– a.k.a. static CMOS
Pull-up OFF
Pull-up ON
Pull-down OFF Z (float)
1
Pull-down ON
X (crowbar)
1: Introduction
0
ACOE419 – Digital IC and VLSI Design
pMOS
pull-up
network
output
nMOS
pull-down
network
31
Series and Parallel




nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON
a
a
0
g1
g2
(a)
(b)
a
g1
g2
(c)
a
g1
g2
b
1: Introduction
0
1
b
b
OFF
OFF
OFF
ON
a
a
a
a
0
1
1
1
0
1
b
b
b
b
ON
OFF
OFF
OFF
a
a
a
a
0
0
b
1
b
0
b
1
1
0
g2
a
b
a
g1
a
0
0
b
(d)
a
0
1
1
0
1
1
b
b
b
b
OFF
ON
ON
ON
a
a
a
a
0
0
0
1
1
0
1
1
b
b
b
b
ON
ON
ON
OFF
ACOE419 – Digital IC and VLSI Design
32
Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
Y
– Requires parallel pMOS
A
B
 Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel
1: Introduction
ACOE419 – Digital IC and VLSI Design
33
Compound Gates
 Compound gates can do any inverting function
 Ex: Y  A B  C D (AND-AND-OR-INVERT, AOI22)
A
C
A
C
B
D
B
D
(a)
A
(b)
B C
D
(c)
C
D
A
B
(d)
C
D
A
B
A
B
C
D
Y
A
C
B
D
Y
(f)
(e)
1: Introduction
ACOE419 – Digital IC and VLSI Design
34
Example: O3AI
 Y  A B C D
A
B
C
D
Y
D
A
1: Introduction
B
C
ACOE419 – Digital IC and VLSI Design
35
Example
 Sketch a transistor-level schematic for a singlestage CMOS logic gate for each of the following
functions:
– (ABC+D)΄
– ((AB+C)D)΄
– (AB+(C(A+B)))΄
1: Introduction
ACOE419 – Digital IC and VLSI Design
36
Signal Strength
 Strength of signal
– How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
– But degraded or weak 1
 pMOS pass strong 1
– But degraded or weak 0
 Thus nMOS are best for pull-down network
1: Introduction
ACOE419 – Digital IC and VLSI Design
37
Pass Transistors
 Transistors can be used as switches
g=0
g
s
s
d
d
g=1
s
g=1
d
s
s
d
s
d
degraded 1
g=0
0
g=1
d
1: Introduction
1
Input
g=0
g
Input g = 1 Output
0
strong 0
Output
degraded 0
g=0
1
ACOE419 – Digital IC and VLSI Design
strong 1
38
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
Input
g
a
b
gb
a
g = 0, gb = 1
a
b
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
a
b
g = 1, gb = 0
strong 1
1
g
g
b
gb
1: Introduction
Output
g
a
b
gb
a
b
gb
ACOE419 – Digital IC and VLSI Design
39
Tristates
 Tristate buffer produces Z when not enabled
EN
A
Y
0
0
Z
0
1
Z
1
0
0
1
1
1
EN
Y
A
EN
Y
A
EN
1: Introduction
ACOE419 – Digital IC and VLSI Design
40
Nonrestoring Tristate
 Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y
EN
A
Y
EN
1: Introduction
ACOE419 – Digital IC and VLSI Design
41
Tristate Inverter
 Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
A
A
EN
Y
Y
Y
EN = 0
Y = 'Z'
EN = 1
Y=A
EN
1: Introduction
ACOE419 – Digital IC and VLSI Design
42
Multiplexers
 2:1 multiplexer chooses between two inputs
S
S
D1
D0
Y
0
X
0
0
0
X
1
1
1
0
X
0
1
1
X
1
1: Introduction
D0
0
Y
D1
ACOE419 – Digital IC and VLSI Design
1
43
Gate-Level Mux Design
 Y  SD1  SD0 (too many transistors)
 How many transistors are needed? 20
D1
S
D0
D1
S
D0
1: Introduction
Y
4
2
4
2
4
2
Y
2
ACOE419 – Digital IC and VLSI Design
44
Transmission Gate Mux
 Nonrestoring mux uses two transmission gates
– Only 4 transistors
S
D0
Y
S
D1
S
1: Introduction
ACOE419 – Digital IC and VLSI Design
45
Inverting Mux
 Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
 Noninverting multiplexer adds an inverter
D0
S
S
D1
D0
D1
S
S
Y
S
S
S
Y
S
D0
Y
S
D1
1: Introduction
ACOE419 – Digital IC and VLSI Design
0
1
46
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
– Or four tristates
D0
S0
D0
S1
0
D1
D1
1
0
Y
Y
D2
0
D3
1
1
D2
D3
1: Introduction
ACOE419 – Digital IC and VLSI Design
47
D Latch
 When CLK = 1, latch is transparent
– D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
– Q holds its old value independent of D
 a.k.a. transparent latch or level-sensitive latch
D
Latch
CLK
1: Introduction
CLK
D
Q
Q
ACOE419 – Digital IC and VLSI Design
48
D Latch Design
 Multiplexer chooses D or old Q
CLK
D
1
CLK
Q
Q
Q
D
Q
0
CLK
CLK
CLK
1: Introduction
ACOE419 – Digital IC and VLSI Design
49
D Latch Operation
Q
D
CLK = 1
Q
Q
D
Q
CLK = 0
CLK
D
Q
1: Introduction
ACOE419 – Digital IC and VLSI Design
50
D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
CLK
CLK
D
Flop
D
Q
Q
1: Introduction
ACOE419 – Digital IC and VLSI Design
51
D Flip-flop Design
 Built from master and slave D latches
CLK
CLK
CLK
QM
D
CLK
QM
Latch
D
Latch
CLK
CLK
Q
CLK
Q
CLK
1: Introduction
CLK
ACOE419 – Digital IC and VLSI Design
CLK
52
D Flip-flop Operation
D
QM
Q
CLK = 0
D
QM
Q
CLK = 1
CLK
D
Q
1: Introduction
ACOE419 – Digital IC and VLSI Design
53
Race Condition
 Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition
CLK1
CLK2
Q1
Flop
D
Flop
CLK1
CLK2
Q2
Q1
Q2
1: Introduction
ACOE419 – Digital IC and VLSI Design
54
Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
 We will use them in this class for safe design
– Industry manages skew more carefully instead
2
1
QM
D
2
2
2
Q
1
1
1
1
2
1: Introduction
ACOE419 – Digital IC and VLSI Design
55
CMOS Fabrication
 CMOS transistors are fabricated on silicon wafer
 Lithography process similar to printing press
 On each step, different materials are deposited or
etched
 Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process
1: Introduction
ACOE419 – Digital IC and VLSI Design
56
Inverter Cross-section
 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors
A
GND
VDD
Y
SiO2
n+ diffusion
n+
n+
p+
p+
n well
p substrate
nMOS transistor
1: Introduction
p+ diffusion
polysilicon
metal1
pMOS transistor
ACOE419 – Digital IC and VLSI Design
57
Well and Substrate Taps
 Substrate must be tied to GND and n-well to VDD
 Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
 Use heavily doped well and substrate contacts / taps
A
GND
VDD
Y
p+
n+
n+
p+
p+
n+
n well
p substrate
well
tap
substrate tap
1: Introduction
ACOE419 – Digital IC and VLSI Design
58
Inverter Mask Set
 Transistors and wires are defined by masks
 Cross-section taken along dashed line
A
Y
GND
VDD
nMOS transistor
pMOS transistor
well tap
substrate tap
1: Introduction
ACOE419 – Digital IC and VLSI Design
59
Detailed Mask Views
 Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal
n well
Polysilicon
n+ Diffusion
p+ Diffusion
Contact
Metal
1: Introduction
ACOE419 – Digital IC and VLSI Design
60
Fabrication
 Chips are built in huge factories called fabs
 Contain clean rooms as large as football fields
Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
1: Introduction
ACOE419 – Digital IC and VLSI Design
61
Fabrication Steps
 Start with blank wafer
 Build inverter from the bottom up
 First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
62
Oxidation
 Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
63
Photoresist
 Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
Photoresist
SiO2
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
64
Lithography
 Expose photoresist through n-well mask
 Strip off exposed photoresist
Photoresist
SiO2
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
65
Etch
 Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
 Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
66
Strip Photoresist
 Strip off remaining photoresist
– Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step
SiO2
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
67
n-well
 n-well is formed with diffusion or ion implantation
 Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
 Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2
n well
1: Introduction
ACOE419 – Digital IC and VLSI Design
68
Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps
n well
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
69
Polysilicon
 Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
70
Polysilicon Patterning
 Use same lithography process to pattern polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
71
Self-Aligned Process
 Use oxide and masking to expose where n+ dopants
should be diffused or implanted
 N-diffusion forms nMOS source, drain, and n-well
contact
n well
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
72
N-diffusion
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks diffusion
 Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
73
N-diffusion cont.
 Historically dopants were diffused
 Usually ion implantation today
 But regions are still called diffusion
n+
n+
n+
n well
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
74
N-diffusion cont.
 Strip off oxide to complete patterning step
n+
n+
n+
n well
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
75
P-Diffusion
 Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+
p+
p+
n+
n well
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
76
Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+
n+
n+
p+
p+
n+
n well
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
77
Metalization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+
n+
n+
p+
p+
n+
n well
p substrate
1: Introduction
ACOE419 – Digital IC and VLSI Design
78
Layout
 Chips are specified with set of masks
 Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
 Feature size f = distance between source and drain
– Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing design
rules
 Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process
1: Introduction
ACOE419 – Digital IC and VLSI Design
79
Simplified Design Rules
 Conservative rules to get you started
1: Introduction
ACOE419 – Digital IC and VLSI Design
80
Inverter Layout
 Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm
long
1: Introduction
ACOE419 – Digital IC and VLSI Design
81
Gate Layout
 Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
 Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
1: Introduction
ACOE419 – Digital IC and VLSI Design
82
Example: Inverter
1: Introduction
ACOE419 – Digital IC and VLSI Design
83
Example: NAND3





Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
1: Introduction
ACOE419 – Digital IC and VLSI Design
84
Stick Diagrams
 Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD
VDD
A
A
B
C
c
Y
GND
INV
1: Introduction
Y
GND
metal1
poly
ndiff
pdiff
contact
NAND3
ACOE419 – Digital IC and VLSI Design
85
Wiring Tracks
 A wiring track is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
 Transistors also consume one wiring track
1: Introduction
ACOE419 – Digital IC and VLSI Design
86
Well spacing
 Wells must surround transistors by 6 l
– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track
1: Introduction
ACOE419 – Digital IC and VLSI Design
87
Area Estimation
 Estimate area by counting wiring tracks
– Multiply by 8 to express in l
40 l
32 l
1: Introduction
ACOE419 – Digital IC and VLSI Design
88
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area
–
Y  A B C D
VDD
A
B
C
D
Y
6 tracks =
48 l
GND
5 tracks =
40 l
1: Introduction
ACOE419 – Digital IC and VLSI Design
89
Example
 Draw a stick diagram and estimate the area for a 4input NOR gate
1: Introduction
ACOE419 – Digital IC and VLSI Design
90
Example
 For a compound gate implementing the boolean
function F=((A+B)C)΄:
– Sketch a transistor-level schematic
– Sketch a stick diagram
– Estimate the area from the stick diagram
1: Introduction
ACOE419 – Digital IC and VLSI Design
91
Summary




MOS transistors are stacks of gate, oxide, silicon
Act as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
 Now you know everything necessary to start
designing schematics and layout for a simple chip!
1: Introduction
ACOE419 – Digital IC and VLSI Design
92
Spice netlist
vdd vdd gnd 5
Vin a gnd pwl 0ps 0 10ns 0 10.5ns 5 50ns 5 50.5ns
0
*** TOP LEVEL CELL: myinv2{lay}
Mnmos@0 y a gnd gnd N L=0.8U W=0.8U AS=3.54P
AD=1.72P PS=8.15U PD=5.8U
Mpmos@0 vdd a y vdd P L=0.8U W=1.6U AS=5.2P
AD=3.54P PS=9.7U PD=8.15U
1: Introduction
ACOE419 – Digital IC and VLSI Design
93