Download 0.13-pixel

0.13mm Pixel Test Chip
Results
Seung Ji, Bob Ely, Daniel Hallberg,
Kevin Einsweiler, M. Garcia-Sciveres
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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2.5mm
0.13mm Test chip
• Submitted in 2004 before FE-I3 design team dissolved.
• Bench tested and comparisons with simulation in 2005
• First radiation tests in 2006 at LBNL 8” cyclotron, using
55MeV p+ and 16 MeV light ions for SEU studies.
• Tentative plans for 20GeV p+ at CERN 10/06.
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Test chip contents 1
•
•
•
•
20 pixel analog section: a 0th order probe of technology issues.
0.25mm enclosed geometry layout redrawn in 0.13mm with no scaling
Layout then adjusted to have a consistent 0.13mm simulation (no DRC
errors and stable operation)
Main adjustment required was to use “low power option” transistors, which
have leakage currents of same order as 0.25mm technology. Otherwise trim
DACS and some current sources could not be implemented.
7
3
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Test chip contents 2
• Digital registers and latches: a test of SEU behavior
Bank of triple redundant latches
Error flag
Parity bit
Common
in
Dedicated out
Shift register (CERN D-flipflops)
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Analog section evaluation
•
•
Scope traces of preamp output of
pixel 0
Comparator output of other 19
pixels allowing threshold “S” curve
scans.
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Analog results summary
•
•
•
Generally works as simulated (not bad considering there was no
performance tuning)
Note, however, that there is no capacitive load at the input and no DC
leakage current. This test chip does not allow to explore these parameters.
Main difference between 0.13mm and 0.25mm is the intrinsic (i.e. untuned)
threshold dispersion
– Average over 5 test chips was 1700e– Value for 0.25mm production chip is 650e-
•
This is crudely understood:
– Low power transistors used have 3x worse matching than regular ones.
– Present manufacturer data on matching is much better than when chip was
submitted.
– Circuit is sensitive to mismatch
– Now expect present models to be able to predict this type of effect
• But models are made for linear transistors
• Not clear how well matching data applies to annular devices.
• Threshold dispersion Monte Carlo simulation not done with present models
•
Noise without detector load:125e- (~same as 0.25mm)
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Irradiations
• All carried out at LBNL 88” cyclotron in 2006
• 55 MeV protons for total dose
– Reached only 70MRad (Si), hoped for 200.
• 16 MeV ions for SEU upset studies
– N, Ne, Ar, Cu, Kr covering LET range 1.2 – 27 MeV/(mg/cm2)
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Irradiation setup
Note analog scan with beam
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Total dose effect on performance - Negligible
Sigma difference (tested on test setup)
12
•
70 Mrad (Si)
• No change in noise (~120e-)
• Threshold dispersion does not
have much to tell us- can’t
measure it in real time
p+/cm2 ~
10
Number of pixels
8
Series1
6
4
2
Sigma difference
Threshold Distribution(Vdd =1,30)
after radiation
40
36
32
28
3.5
3
2.5
2.5
2
Series2
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50
00
46
00
(e)
electrons
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
42
00
38
00
30
00
26
00
10
00
50
00
46
00
42
00
electrons
34
00
(e)
38
00
34
00
30
00
0
26
00
0
22
00
1
0.5
18
00
1
0.5
22
00
1.5
18
00
Series1
14
00
2
1.5
# of pixels
3
14
00
# of pixels
electrons
Threshold Distribution(Vdd =1.30V)
before radiation
3.5
10
00
24
20
16
12
8
4
0
-4
-8
-12
-16
-20
0
-24
5x1014
9
Various latch designs tested for SEU
#0: CERN rad hard D-flip-flop
#1: Cross coupled “DICE” latch
using standard cell inverters
#2: Custom drawn conventional
latch
#3: Cross coupled “DICE” latch
using custom drawn
inverters
#4: Artisan library D-flip-flop
#5: Scaled version of pixel
production chip global
register.
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Single latch LET threshold results
Cross Section (cm2)
10-7
10-8
10-9
Latch type
10-10
10-11
Types 3 & 5 had insufficient upset rates.
28 SEP 06
0
1
2
4
CRN-D
x-std
cst-D
art-D
0->1 threshold
MeV/(mg/cm2)
2.3
7.5
2.0
0.1
1->0 threshold
MeV/(mg/cm2)
7.0
7.2
7.0
1.0
0->1 x-section
x10-9cm2
44
+/-4
18
+/-2
60
+/-6
33
+/-3
1->0 x-section
x10-9cm2
44
+/-4
23
+/-3
35
+/-3
12
+/-2
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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About triple redundant cells
• Consider first ideal case of single latches completely independent,
and ion energy deposition point-like.
• In this case, rate of triple redundant cell upsets is a calculable
probability problem, given single latch cross section.
• By comparing measurement and calculation we test the initial
assumption
• We expect this assumption to hold for slow ions (no d-rays or
showers).
• We expect (based on .25u pixel chip) that high energy hadrons
would instead produce showers that introduce correlations (upset
two neighbor latches with same shower)- but this irradiation has not
been done yet!
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Triple redundant prediction
• (For each test all latches were “prepared” in a pure 0 or 1 state)
• For small time the number of single latches upset vs. time is
approximately linear, U(t) ~ 3NFst (U(t)<<3N)
• Only triplets with one upset latch are candidates to produce a triple
redundant error (TRE). The rate of TRE is therefore,
E(t) ~ 2(3NFst).Fst = 6N(Fst)2 (E(t)<<N)
– This is only the first order term. In reality,
U(t) = 3N[s1/(s1+s2)](1-e-F(s1+s2)t), and E(t) still more complicated,
– But interesting behavior (correlations) are present at lowest order.
• Plot absolute prediction (6N(Fst)2) together with data of TRE vs.
fluence for small t (N is in the range 224-266)
• The way TRE’s were counted was by monitoring the parity function
for each chain of triple redundant registers.
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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TRE data vs. prediction
(for all 0 initial state)
CERN-D
X-std
Cust-D
Art-D
-1s
+1s
-1s
+1s
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LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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SEU interpretation
• Expectation that upsets in single cells from ions are uncorrelated is
generally confirmed.
• Register 2 discrepancy could be due to counting technique used, but
otherwise not understood
– (Two upsets within a single sampling period lead to no change in parity)
• Extreme hardness of DICE cross-coupled cells can also be
understood in term of the point-like, independent nature of slow ions
– Writing a DICE cell requires a simultaneous signal on 2 different nodes
• We now need 20GeV p+ results, which involve extended energy
deposits leading to correlations in SEU and upsets of DICE cells
– as observed in present 0.25u generation, but
– Quantitative results for 0.13u would be very interesting.
• Note that TR by itself is not a cure for SEU. For long term storage
TR must be coupled with error correction on a “short” time scale,
defined by 2Fst << 1
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Conclusions
• Useful lessons for next generation deep sub-micron pixel
chip
• Matching is a critical issue that must be addressed from
the start
• Some steps to quantifying SEU effects for different latch
implementation options.
Future work
• Possible SEU run at CERN 20 GeV p+ beam (coll. with CPPM)
• Next iteration 0.13 test chip
– Focus on New, ground-up, amplifier design
• Simulation of dispersion as a design tool
– Address charge measurement with higher occupancy
– Feb 07 target submission
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Backup Slides
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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TRE vs. fluence for large t
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Weibull Function used
X-section
(y-axis)
Saturation
value of
x-section
LET
(x-axis)
Threshold
value
Exponent
(slope parameter)
Width
paramater
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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1->0 single latch LET results
10-7
Cross Section (cm2)
10-8
10-9
10-10
10-11
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
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Bias mirror voltages
•
No change (after 2 week cool-down)
1.3V
Before (V)
After (V)
Difference
AITrimIF
0.582
0.581
-0.001
AITrimTh
0.645
0.645
0
AID
0.953
0.957
0.004
AIF
0.524
0.521
-0.003
AIL
0.736
0.739
0.003
AIL2
0.564
0.563
-0.001
AIP
0.632
0.634
0.002
AIP2
0.979
0.984
0.005
AIVDD
1.01
1.014
0.004
AIOUT
0.511
0.511
0
28 SEP 06
LECC 06 -- 0.13u pixel test chip -- M.Garcia-Sciveres
Vbias
100uA
21