Download Analysis and Synthesis Algorithms 1

Topics

Circuit design for FPGAs:
– Logic elements.
– Interconnect.
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Multiplexers as logic elements
1
Q
A
CLR
1
0
0
D
(AB)’
A^B
latch
A
CLR
0
1
B
0
0
CLK
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Using antifuses
FPGA-Based System Design: Chapter 3
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Static CMOS gate vs. LUT

Number of transistors:
– NAND/NOR gate has 2n transistors.
– 4-input LUT has 128 transistors in SRAM, 96 in
multiplexer.

Delay:
– 4-input NAND gate has 9t delay.
– SRAM decoding has 21t delay.

Power:
– Static gate’s power depends on activity.
Copyright  2004 Prentice Hall PTR
– SRAM
always
burns power.
FPGA-Based System
Design: Chapter
3
Lookup table circuitry

Demultiplexer or multiplexer?
adrs
adrs
LUT
FPGA-Based System Design: Chapter 3
LUT
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Traditional RAM/ROM

Cell drives long bit line:
Bit line
adrs
FPGA-Based System Design: Chapter 3
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Lookup memory

Multiplexer presents smaller load to
memory cells.
– Allows smaller memory cells.
FPGA-Based System Design: Chapter 3
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Multiplexer styles
static gates
FPGA-Based System Design: Chapter 3
pass transistors
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Multiplexer design
Pass transistor multiplexer uses fewer
transistors than fully complementary gates.
 Pass transistor is somewhat faster than
complementary switch:

– Equal-strength p-type is 2.5X n-type width.
– Total resistance is 0.5X, total capacitance is
3.5X.
– RC delay is 0.5 x 3.5 = 1.75 times n-type
switch.
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Static gate four-input mux




Delay through ninput NAND is
(n+2)/3.
Lg b + 1 inputs at
first level, so delay
is (lg b + 3)/3.
Delay at second
level is (b+2)/3.
Delay grows as b
lg b.
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Pass-transistor-based four-input mux

Must include decode
logic in total delay.
FPGA-Based System Design: Chapter 3
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Tree-based four-input mux


Delay proportional to
square of path length.
Delay grows as lg b2.
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
LE output drivers

Must drive load:
– Wire;
– Destination LE.

Different types of wiring present different
loads.
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Avoiding programming hazards

Want to disable connections to routing
channel before programming.
From LE
config
progb
Routing channel
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Interconnect circuits

Why so many types of
interconnect?
– Provide a choice of
delay alternatives.

Sources of delay:
– Wires.
– Programming points.
FPGA-Based System Design: Chapter 3
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Styles of programmable
interconnection point
pass transistor
FPGA-Based System Design: Chapter 3
Three-state
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Pass transistor programmable
interconnect point



Small area.
Resistive switch.
Delay grows as the
square of the number
of switches.
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Three-state programmable
interconnection point


Larger area.
Regenerative driver.
+
FPGA-Based System Design: Chapter 3
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Switch area * wire delay vs. buffer
size (Betz & Rose)
© 1999 IEEE
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Switch area * wire delay vs. pass
transistor width (Betz & Rose)
© 1999 IEEE
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Wire delay vs. switch sizes (Chandra
and Schmidt)


Delay vs. switch
size for various
driver sizes.
U-shaped curve:
– Resistance
initially
decreases.
– Increased
capacitance
eventually
dominates.
© 2002 IEEE
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Clock drivers

Clock driver tree:
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
Clock nets
Must drive all LEs.
 Design parameters:

– number of fanouts;
– load per fanout;
– wiring tree capacitance.

Determine optimal buffer sizes.
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
H tree

Regular layout
structure.
– Recursive.
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR