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CMOS Analog Integrated Circuits:
Models, Analysis, & Design
Dr. John Choma, Jr.
Professor of Electrical Engineering
University of Southern California
Department of Electrical Engineering-Electrophysics
University Park; Mail Code: 0271
Los Angeles, California 90089-0271
213-740-4692 [OFF]
626-915-7503 [HOME]
626-915-0944 [FAX]
johnc@almaak.usc.edu (E-MAIL)
EE448
MOS Circuit Level Models
Fall 2001
Lecture Overview
•Static Model
Cutoff Region
Ohmic (Triode) Region Model
Saturation Region Model
Subthreshold Model
•Short Channel Effects In Saturation
Channel Length Modulation
Substrate/Bulk Phenomena
Mobility Degradation
Carrier Velocity Saturation
•Small Signal Model In Saturation
Forward Transconductance
Bulk Transconductance
Capacitances
•Sample Circuit Analysis (Inverter)
Gain
Bandwidth
2
N–Channel MOSFET
Ld
L
S
Ld
G
D
Silicon Dioxide
Tox
N+
Source
N+
Drain
Xd
P–Type Substrate
(Concentration = ND cm-3
)
B

d
V

gd
Ig
Ig 
b

B

V
gs
Is = Id +Ig +Ib
I
G


I
D
I
s
Vds
Ib 
V
Is 
bs


0, for
S
V ds
0
V bs < 0
Id
= V gs – V gd
3
P–Channel MOSFET
Ld
L
S
Ld
G
D
Silicon Dioxide
Tox
P+
Source
P+
Drain
Xd
N–Type Substrate
(Concentration = ND cm-3 )
B

Vdg

G

I
I
I
b


B

sg
Ig
d
g
V
Is = Id +Ig +Ib
D
I
s
Vsd
V

0, for
Is
sb

Ib

S


0
V sb < 0
Id
V sd = V sg – V d g
4
Characteristic Curves: Cutoff And Ohmic Regimes
l
l
l
Cutoff Regime: Vgs < Vhn
 Id = 0
 V hn 
Threshold Voltage, Function Of Bulk–Source Voltage
Ohmic Regime:
V gs  V hn

Id

K n = µ n C ox =
= Kn
W
L
V ds
and
V ds
V ds
V gs – V hn –
2
µ n  ox
T ox
< V gs – V hn
(Hundreds Of µmhos/Volt)
Comments

W/L Is Gate–Channel Aspect Ratio, A Designable Parameter
 Vds = Vgs – Vgd < Vgs – Vhn Implies Vgd > Vhn
 Temperature Effects (Holes And Electrons):µ(T)

µ(To)
/
3 2
Resistance For Small Drain–Source Voltage:

 Id
V ds

To
T
1
R ds
= Kn
W
L
V gs – V hn – V ds
=
Id
V ds
V gs – V hn – V ds
V gs – V hn –
V ds
2

Id
V ds
5
Characteristic Curves: Saturated Regime
l
Kn
2

Id

V dss

l
Saturation Regime:
V gs – V hn

I dss
=
Kn
2
=
W
L
W
L
V gs  V hn
V gs – V hn
V ds 
&
V gs – V hn
2
 Drain Saturation Voltage
2
V dss
 Drain Saturation Current
Comments
 Square Law Voltage–Controlled Current Source
 Drain Current Shows Negative Temperature Coefficient
Because Of Its Proportionality To Mobility
 Differential Current Of Two Matched Devices Is Linear With
VDM
Differential Gate–Source Voltage
, Provided Common Mode
VCM
Gate–Source Voltage
Is A Constant
I d1 – I d2
=
Kn
2
W
L
I d1 – I d2
= Kn
W
L
I d1 – I d2
= Kn
W
L
V gs1 – V hn
V gs1 + V gs2
2
V CM – V hn
2
–
– V hn
V DM
V gs2 – V hn
2
V gs1 – V gs2
6
Simple Differential Pair
R
–
Vo
Id1
l Inputs
+VDD
c
R
V gs1
= V CM +
V DM
2
Id2
V gs2
= V CM –
V DM
2
+
c
VDM
2
+
M1
c
M2
–
–
VDM
+
Vgs1 + Vgs2
= 2 VCM
Vgs1 – Vgs2
= V DM
2
c
+
VCM
–
l Response
I d1 – I d2
= Kn
W
L
V o = R I d1 – I d2
l
V CM – V hn
= Kn R
W
L
V DM
V CM – V hn
V DM
Note Differential Output Current And Voltage Are Linear With Respect
To Differential Input Voltage Without Invoking Small Signal Approximation
6a
Characteristic Curves: Subthreshold Regime
l
Subthreshold Regime:
VT =
s
1.2 < n
s
l
kT
q
s
Vgs
< Vhn + 2 n VT & Vds
• 3 VT
= 26 mV @ 27 8C
< 2.0
I d = 2K n
W
L
n VT

2
e
( V gs – V hn ) n V T
/
Comments
Bipolar Type I–V Action Indigenous To Subthreshold Regime
s Subthreshold Operation Corresponds To Gate–Channel Interface
Potentials Lying Between One And Two Fermi Potentials
s Useful Only For Low Speed, Low Power Applications
s
7
Sample Simplified MOS Static Characteristics
Drain Current (microamperes)
700
5 volts
600
500
Drain
Saturation
Current
Ohmic
Regime
400
Kn
4 volts
300
= 80 µmho/volt
V hn = 1.2 volts
Saturation
Regime
200
W
L
3 volts
100
Gate-Source Voltage = 2 volts
0
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
4.4
4.8
Drain-Source Voltage (volts)
8
Cutoff Regime
V

S
ds

V

c
gs

G
l
D
SiO 2
Depletion
V ds
I
d
 0
0 < V gs < V hn
V bs  0
Fixed
Immobile
Charges
DEPLETION
LAYER, V ds  0
DEPLETION
LAYER, V ds = 0
P–Type Substrate

V
bs
l Zero Current
N+
Drain
N+
Source
            
l
Vgs
l
V ox  Voltage Across
l
Vy 
= Vox + Vy
Oxide
Interface
Potential

B
9
Channel Inversion: Ohmic Regime
G
S
D
V gs
P–Type
Substrate
V ds
> V hn
= 0
L
G
S
D
V gs > V hn
0  V ds 

Vdss
  DVds
L'
V gs – V hn
V gd > V hn

DL
P–Type
Substrate
Metal or Polysilicon
Inversion Layer
Silicon Dioxide
Depletion
10
Channel Inversion: Saturation Regime
G
S
D
V gs > V hn
0  V ds
P–Type
Substrate
= V gs – V hn
V gd 
V hn
L
G
S
D
V gs > V hn
0
V ds
> V gs – V hn
V gd < V hn

Vdss
  Vds

L
L'
P–Type
Substrate
Metal or Polysilicon
Inversion Layer
Silicon Dioxide
Depletion
11
Channel Length Modulation
G
S
D

Vdss
  V
ds
L'
l
Id
|
l
V

DL
Modified Saturation Regime Current
= I dss
V ds > V dss
L
L – L
=
Kn
2
W
L
V gs – V hn
2
1 +
V ds – V dss
V
Channel Modulation Voltage
= L
2 q NA
s
V ds – V dss + V j
(Typically Under 20 Volts And
As Small As 1/3 Volt For Deep
Submicron MOSFETs)
Vdss
Vj =
= Vgs – V hn
ND NA
kT
ln
q
2
N iB
12
Channel Length Modulation Parameters
l
Id
|
Modified Saturation Regime Current
= I dss
V ds > V dss
Vdss
Vj =
L
L– L
=
Kn
2
W
L
= Vgs – V hn
ND NA
kT
ln
q
2
N iB
V = L
V gs – V hn
2 q NA
s
2
1 +
V ds – V dss
V
V ds – V dss + V j
l
Parameters
 N A  Average Substrate Impurity Concentration
es

 Dielectric Constant Of Silicon (1.05 pF/cm)
q

 Electronic Charge Magnitude
Vl

 Channel Length Modulation Voltage
Vj

 Built In Substrate–Drain/Source Junction Potential
l
Note
 Large Channel Length Reduces Channel Modulation
 Small Substrate Concentration Increases Channel Modulation
13
Substrate/Bulk Phenomena
l
Effect On Threshold Voltage


l
l
Id =
Kn
2
W
L
V gs – V hnc

V =

V F = V T ln
2
C ox
1 +
V VF – VT
V h = V ho + 2
q N A s
2
= q NA 
NA
N iB
T ox
s
ox
V ds – V dss
V
1 –
2
V bs
2 VF – VT
– 1
(High Hundreds Of µVolts
(Few Tenths Of Volts)
Parameters
 VF  Fermi Potential; Renders Channel Surface Intrinsic
N iB  Intrinsic Carrier Concentration In Substrate


ox  Dielectric Constant Of Silicon Dioxide (345 fF/cm)
Note
 Small Oxide Thickness Reduces Threshold Modulation
 Small Substrate Concentration Reduces Threshold Modulation
14
Threshold Voltage Modulation
Threshold Correction (volts)
0.7
0.6
Oxide Thickness = 1,500 A
0.5
N iB = 10
10
cm
–3
;
N A = (10)
14
cm
0.4
–3
0.3
750 A
0.2
0.1
50 A
100 A
0
-6
-5
-4
-3
-2
-1
0
Bulk–Source Voltage, Vbs (volts)
15
Mobility Degradation Due To Vertical Field
l
Electric Field Problems
 Thin Oxide Layers Conduce Large Gate -To- Channel Fields
For Even Small -To- Moderate Gate–Source Voltages
 These Enhanced Fields Impart Increasing Energies To Carriers,
Thereby Causing More Carrier Collisions And Degraded Mobilities
l
Mobility:
V gs – V hnc
VE
1 +
VE
l
µn

µ neff

6
(500)(10 ) T ox
(Low Hundreds Of Volts)
Parameters
 µneff  Effective Carrier Mobility In Channel
 VE  Vertical Field Degradation Voltage Parameter
 Crude One Dimension Approximation To Two Dimensional Problem
VE
 T ox in MKS Units Yields
In Volts
16
Impact Of Mobility Degradation
l
Static Drain Current
K n = µ n C ox  K neff


l
Id =
Kn
2
W
L
= µ neff C ox
V gs – V hnc
2
1 +
V ds – V dss
V
V gs – V hnc
1 +
VE
Other Effects
 Reduced Bandwidth And Increased Carrier Transit Time
 Smaller Current For Given Gate–Source Bias
 Reduced Forward Transconductance
17
Mobility Degradation Due To Lateral Field
l
Electric Field Problems
 Short Channels Conduce Large Drain -To- Source Fields
For Even Small -To- Moderate Drain–Source Voltages
 These Enhanced Fields Impart Increasing Energies To Carriers,
Thereby Causing More Carrier Collisions And Degraded Mobilities
 At Very Large Horizontal Fields, Carrier Velocities Ultimately
Saturate To A Value vOf
, Which Is About 0.1 µm/pSEC
sat
 Saturation Occurs When Horizontal E
Field,
,Equals Or Exceeds A
h
Ec
Critical Value,
, Which Is About 5 V/µm
l
Mobility And Field
µn

µ ne 
Eh
1 +



=
v sat
Ec + Eh
Ec
v sat = µ n E c
v = µ ne E h
Eh


V gs – V hn
L
µn E h
Eh
1 +
Ec
18
Velocity – Mobility – Field Relationships
Carrier Velocity (µm/psec)
0.1
Normalized Carrier Mobility
1
0.09
0.9
Carrier Velocity
0.08
0.8
0.07
0.7
0.06
0.6
0.05
0.5
0.04
0.4
Normalized Mobility
0.03
0.3
0.02
0.2
0.01
0.1
0
0
0
5
10
15
20
25
30
35
40
45
50
Lateral Electric Field (V/µm)
18a
Mobility And Lateral Field
l
Mobility And Field


l
µ ne
Eh


µn
Eh
1 +
Ec
V gs – V hnc
L

=
µn
V gs – V hnc
1 +
L Ec
=
µn
V dss
1 +
L Ec
V dss
L
Electric Field Problems
Eh
 Crude Approximation For Horizontal Field,
 Free Carriers Exist Only Over Channel Where Voltage With
Vdss = Vgs – Vhnc
Respect To The Source Is At Most
 Channel Length, L, Should Be Effective Channel Length, L',
But This Shrinkage Is Already Accounted For By Channel Length
Modulation Voltage Parameter,
V
 L E c Is About 1.75 Volts For L = 0.35 µm
19
Volt–Ampere Impact Of High Lateral Field
l
Static Drain Current
K n = µ n C ox  K neff

= µ neff C ox
2

l
Kn
2
W
L
1 +
V ds – V dss
V
V gs – V hnc
1 +
L Ec
Very High Fields


l
Id =
(Vgs – V hnc )
Vgs – Vhnc
Id

>> L E c
W C ox v sat
2
V gs – V hnc
1 +
V ds – V dss
Vl
Comments
 Drain Current Scales Approximately With W, As Opposed
To W/L
 Drain Current Almost Linear W/R To Gate–Source Voltage
20
MOS Large Signal Model
D
Cold
id
c
rdd
Cgd
c
Static Drain Current
c
c
DBD
c
rdb
Id
G
c
C gd
 Gate-Drain Capacitance
C gs
 Gate-Source Capacitance
C db
 Drain-Bulk Capacitance
C sb
 Source-Bulk Capacitance
C old
 Drain Overlap Capacitance
Cdb
DBS
c
c
c
c
c
B
r ss
 Source Overlap Capacitance
 Drain Ohmic Resistance
 Source Ohmic Resistance
r bb
 Bulk Ohmic Resistance
 Bulk-Drain Diode
r sb
 Bulk-Source Diode
r db
 Bulk Spreading Resistance
 Bulk Spreading Resistance
rsb
Cgs
rss
c
rbb
Csb
Cols
C ols
r dd
S
DBD
DBS
21
Device Capacitances In Saturation
D
Cold
C gd + C old
id

C old
c
rdd
Cgd
c
C gs
c
c
DBD
c
rdb
C db
Id
G
= W L C ox
=
Cdb
DBS
c
c
c
c
c
rsb
Cgs
rss
c
B
rbb
C sb
1 –
 Large (Hundreds Of fF)
C sb
 Large (Hundreds Of fF)
 Moderate (High Tens Of fF)
C gd , C old , C ols
 Small (Tens Of fF)
V bd
Vj
V bs
Vj
C ols
= W L d C ox
Ad
 Drain-Bulk Junction Area
 Source-Bulk Junction Area
 Zero Bias Depletion
S
C db
Ld
L
As + W L C jo
Csb
Cols
C gs
=
+
Ad C jo
1 –
c
2
3
= W L d C ox
As
C jo
Capacitance Density
22
Approximate (Long Channel) Small Signal Model
C old
g mf
D
Cgd
Cdb
c
c
c
c
gmf vga
gmb vba
go
Cgs
Csb
c
c
c
vga
+

c

vba
c
b =
+
go
c
B

C ols
S

g mb
G

c
I d
V gs |
I d
V bs |

2K n
W
L
I dQ
Q
= b g mf
Q
V/ 2
2 V F – V T – V bsQ
I d
V ds |

Q
I dQ
V  + V ds – V dss
Assumptions
l




All Series Ohmic Resistances Are Negligible
Transistor Operates In Saturation Regime
"Long Channel" Approximation Invoked For Static Drain Current
Model To Be Used As A Precursor To Computer–Based Studies
23
Short Channel Small Signal Model
l Drain Current:
Id =
Kn
2
W
L
l Intermediate Parameters:
l Forward
Transconductance: g mfs
l Output Conductance:
2
1 +
V ds – V dss
V
V gs – V hnc
1 +
L Ec
V ds – V dss
V
f =
f
W
L
c
=
V dss
LEc
g mf =
2Kn
b =
V/ 2
2 V F – V T – V bsQ
= g mf
l Bulk Transconductance:
V gs – V hnc
1+f
1+f c
1–
I dQ
V dss / 2 V 
f 2
– c/
1+f 
1+f c
g mbs = b g mfs
go =
I dQ
V  + V ds – V dss
24
Hypothetical Device
l Physical Parameters
N A = 5 (10)
14
cm
N D = 5 (10)
20
cm
N iB = (10)
10
cm
l Device Parameters
–3
T ox = 50 Angstroms
–3
L = 0.35 µm
–3
Vhn = 0.65 volts
 s = 1.05 pF/cm
 ox = 345 fF/cm
µn = 400 cm 2 / volt-sec
E c = 4 volts / µm
T = 300 8K
W/ L = 5
l Circuit Parameters
Vds = 2 volts
Vgs = 1.2 volts
Vbs = –3 volts
25
Static Performance
l Peripheral Calculations
VF = 280.0 mV (Fermi Potential)
Vj = 917.4 mV (Junction Potential)
Vu = 176.4 µV (Body Effect Potential)
V hnc = 685.2 mV (Compensated Threshold) 
V hn = 35.2 mV
Vdss = 514.8 mV (Drain Saturation Voltage)
V = 669.7 mV (Channel Length Voltage)

L E c = 1.4 volts (Lateral Field Voltage)
K n = 276.0 µmho / volt
(Transconductance Parameter)
f = 2.218 (Channel Length Parameter)

f c = 0.368 (Lateral Field Parameter)
l
Static Drain Current
 I d = 182.9 µA (Long Channel Drain Current)
 I d = 430.2 µA (Short Channel Drain Current)
 Note Short Channel -To- Long Channel Ratio of 2.35; Ratio Is
Generally Between 1.5 And 3.0
26
Small Signal Parameters
l
Forward Transconductance
 gmf = 1.09 mmho (Ignoring Short Channel Effects)
 gmf = 1.25 mmho (Incorporating Short Channel Effects)
 Note Short Channel -To- Long Channel Ratio of 1.14; Ratio Is
Generally Between 0.5 And 2.0
l
Bulk Transconductance
(Bulk Parameter)
 b = 5.0 2 (10) –3
 gmb = 6.25 µmho (Incorporating Short Channel Effects)
 Note Bulk Transconductance Is About 200 Times Smaller
Than Forward Transconductance
l
Drain–Source Conductance
 go = 199.7 µmho (Incorporating Short Channel Effects)
 Corresponds To Shunt Output Resistance Of About 5 K
 Mandates Conductance Enhancement Strategies When
Designing High Performance Transconductors
27
Device Unity Gain Frequency
D
V
dd
Cgd + Cold
AC Short Circuit
c
c
I
bias
Cbig
g
c
mf
c
i in
l
l
i out
c
i out
i in
T
=

c
c
v
g
1
go
v
mb 2
i out
c
Cgs + Cols
i in
G+
v
1
 S 
v
2
+
B
g mf – s C gd + C old
s C gs + C ols + C gd + C old
C gs
g mf
+ C ols + C gd + C old

µ n V gs – V hn
3L d
2 2
L
+
3
L
l Comments
 Unity Gain Frequency Is Good Device Figure Of Merit;
Crude Circuit Performance Figure Of Merit
 Result Assumes  T C gd << gmf
28
Common Source Inverter
ML
c
VDD
R Leff
c
c
+
Vs
VGG
–
+
c
Vo
MD
R Leff
c
Vos
MD
CL
CL
c
+
Vs
c
–
–
Schematic Diagram
AC Schematic Diagram
29
Inverter Load Resistance Calculations
rddl
ML
c
c
c
+
Vx
–
g mbl vba
g mfl vga
Ix
+ vga –
c
c
rol
c
– vba +
rssl
rbbl
+
Vx
v ga
Vx =

R Leff
Vx
Ix
= v ba
r ssl + r ddl
= r ssl +
–
Ix
= – V x + r ssl I x
I x + r ol I x + g mfl v ga + g mbl v ba
1 +
r ddl + r ol
1 +  bl g mfl r ol

1
1 +  bl g mfl
30
Inverter Gain Calculations
R'
c
R Leff
c
c
rddd
Vos
MD
Vs
c
+ vga –
–
g mfd vga
Vs
V os
Vs
= –
1 +
R Leff
CL
c
c

c
– vba +
rssd
rbbd
–
gmfd R Leff
R Leff + r ddd + r ssd
1 + bd gmfd r ssd +
r od
Av
Ignore For
Low
Frequencies
rod
g mbd vba
+
Av =
Vos
c
c
CL
+
R out
–
1
1 +  bl

– gmfd R Leff

–
gmfd
1 + bl gmfl
Wd /L
Wl/L
31
Inverter Bandwidth Calculations
+
rddd
R'
Vx
–
Ix
c
g mfd vga
+ vga –
c
rod
g mbd vba
c
c
– vba +
rssd
B 3dB =
R

Vx
Ix
=
1
R Leff C L
R out C L
1
=
R
/
| R Leff C L
= r ddd + r ssd +

1 +  bl g mfl
CL

1
R Leff C L
1 + 1 +  bl g mfd r ssd r od
GBP

B 3dB
/
1
rbbd
A v B 3dB
=
g mfd
CL
32