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İSTANBUL TECHNICAL UNIVERSITY
ELECTRICAL ELECTRONICS ENGINEERING FACULTY
OTP ROM Macro Design for AMS 0.35um CMOS Process
B.Sc Thesis by
Emrah YASAN
(040050319)
Department: Electronics and Communication Engineering
Programme: Electronics Engineering
Supervisor: ASSIS. PROF.DR DEVRİM YILMAZ AKSIN
MAY 2010
i
TABLE OF CONTENTS
SYMBOLS
v
ÖZET
vi
SUMMARY
vii
1. INTRODUCTION
1
1.1 Introduction
1
1.2 Motivation
2
1.3 The Floating Gate
3
1.3.1 Basic Concepts of the Floating Gate
3
1.3.2 Tunneling Mechanism
4
1.3.3 Challenge of Burning Floating Gate
5
1.3.4 The Challenge of Determining Logic Values
6
2. CIRCUITS
7
2.1 Unit Cell
7
2.1.1
Unit Cell Circuit
7
2.1.2
Unit Cell Modeling
9
2.2 Output Node Controller (ONC)
12
2.2.1
Circuit of Output Node Controller
12
2.2.2
Test Circuit of Output Node Controller
15
2.2.3
Simulation Results of Output Node Controller
15
2.2.4
Comments On Test Results
18
2.3 Read Comparator (RC)
19
2.3.1
Circuit of Read Comparator
19
2.3.2
Test Circuit of Read Comparator
22
2.3.3
Simulation Results of Read Comparator
22
2.3.4
Comments on Test Results
23
2.4 Bank Select or Supply Level Translator (SLT)
ii
24
2.4.1
Circuit of Bank Select
24
2.4.2
Test Circuit of Bank Select
26
2.4.3
Simulation Results of Bank Select
27
2.4.4
Comments on Test Results
29
2.5 Decoder
30
2.5.1
Circuit of Decoder
30
2.5.2
Test Circuit of Decoder
32
2.5.3
Simulation Results of Decoder
33
2.5.4
Comments on Test Results
36
2.6 State Machine
37
2.7 Complete Circuit of the OTP ROM
38
3. CONCLUSION
40
REFERENCES
41
ADDENDUM
42
BIOGRAPHY
49
iii
ACKNOWLEDMENT
I have the pleasure to thank ASSIS. PROF.DR DEVRİM YILMAZ AKSIN, my
thesis supervisor for his support and guidance.
I would like to dedicate this thesis to my family for all their support.
May 2010
Emrah YASAN
iv
SYMBOLS
Ф: Injection barrier height at the interface
h: Planck’s constant
ћ: h/2
E: Electric Field
q: charge of a single electron (1.6 x 10-19 C)
m: mass of a free electron (9.1 x 10-31 kg)
v
ÖZET
Bu bitirme çalışması; bir kez programlanabilir ROM’un tasarımını ve
simülasyonlarını içermektedir. Çalışmada ilk olarak quantum tünellemesi kullanan
―Floating Gate‖ teknolojisi ile bir tane birim hücre tasarlanmıştır. Bu teknolojide
yüksek gerilime dolayısı ile yüksek elektromanyetik alana maruz kalan elektronların
birikmesi sonucu eşik değeri düşen mosfetler sözkonusudur. Elektronların quantum
tünnellemesi ile birikmesi mosfeti açık konumuna getirecek kullanılan PMOS ise
direnç gibi davranacaktır. Böylece yakılan mosfet direnç gibi davranacak ve savak
terminalinde bir gerilim oluşturacaktır. Fakat yakılan ya da programlanan mosfetin
yaklaşık 30000 Ohm civarında direnç göstermesi birim hücrenin çıkışındaki gerilim
değerinin çok düşük olmasıne sebeb olacaktır. Bu yüzden bir diferansiyel yapı terçih
edilmiş böylece okuma zorluklarına karşı bir çözüm edilmiş oldu.
Bir sonraki aşamada ise bilgiyi saklayacak olan mosfetlerin kontrolunu sağlayacak
olan bir düğüm kontroloru (ONC) tasarlanmıştır. Ilerleyen aşamalarda tek bir durum
makinasının kullanımı uygun görüldüğü için ONC kullanımından vazgeçilmiştir.
Diferansiyel yapının çıkışına karar verilmesi için bir de karşılaştırıcı tasarlanmıştır.
Daha sonraki aşamalarda, daha önceden bahsedildiği gibi ―Floating Gate‖ mosfeti
programlamak için yüksek (yaklaşık 7 V) bir gerilim sözkonusudur. Fakat, bu
gerilimlerde diğer bankları kapatmak 3.3 volta cıkabilen bir sistemle mümkün
olmayacaktır. Çünkü kaynak terminalinden 7V beslemesi olan bir P tipi bir mosfetin
3.3 V ve altındaki gerilim değerleriyle kapatmak mümkün değildir. Bu yüzden
gerilim transfer edici veya bank seçici adıyla 7V gerilimin altında istenmeyen
bankları kapatacak bir devre tasarlanmıştır. Bellek tasarımın doğal bir sonucu olarak
bir adet adres çözücü tasarlandı.
Son olarak bu yapıları, yazma ve okuma durumlarında kontrol etmek amacıyla
Verilog HDL kullanılarak bir durum makinası yazıldı.
Tüm bi yapıların birleştirilmesi sonucu olarak, tek bir kez programlanabilir ROM
(OTP ROM) yapısı ortaya çıkmış oldu.
vi
SUMMARY
In this thesis, a one time programmable read only memory (OTP ROM) is designed
and simulated.
First of all, a unit cell that uses quantum tunneling mechanism with floating gate
technology. In this technology, if an electron exposed to high voltage, therefore high
electromagnetic field, these electrons tunnel trough and make threshold voltage
decrease. And then, this mosfet behaves as resistor. A voltage level is going to occur
at the drain node of the resistor that behaves as a closed switch. However this resistor
is approximately equal to 30000 Ohm. Having high resistance causes voltage
dropping. Therefore, a differential structure is chosen to solve reading problems.
Secondly, to control the mosfets that keep the data a output node controller (ONC) is
designed. However, after designing the state machine there is no need for ONC.
A comparator is designed for determine the output of the differential unit cell. As
stated before, to programme a Floating gate mosfet a high voltage (approximately
7V) is needed. But at that voltage levels, there is no change to close unwanted banks
due to having maximum 3.3V. Therefore, a voltage level translator is designed to
close the PMOSs. In consequence of designing a memory, a decoder is designed.
Finally, to control the internal signals a state machine designed by using Verilog
HDL language.
Eventually, by connecting all these modules, a OTP ROM is occurred.
vii
Introduction
1.1 Introduction
Complementary metal-oxide-semiconductor (CMOS) memories can be categorized
as random access memories (ROM) and read only memories (ROM) [1]. The main
difference between ROM and RAM memories is volatility. RAM is volatile memory
type because it losses it data when power supply is switched off and ROM is
nonvolatile that keeps stored information even there is no power supply[1].
In this graduation project, a read only memory (ROM) that can be programmable
only once is designed and simulated. A ROM that can be programmed only once is
called one time programmable read only memory (OTP ROM).
Generally there are three ways to program or to burn OTP ROMs. The first one is to
blow a Fuse resistor. The second one is to blow the thin oxide fuse and the last one is
to use floating gate.
Fuse technology uses blown a resistor. The blowing the thin oxide uses gate oxide
breakdown. Applying the high voltage between gate and source terminals of the
mosfet blows the capacitor and there is a resistor is occurs instead of capacitor’s
stead. The last one is floating gate that uses Fowler- Nordheim tunneling mechanism.
Read only memory is being more commonly used due to being cheap, fast and nonvolatile. However, conventional ROMs offer no flexibility to programmer after being
produced at factory because well-known conventional ROMs are programmed at
factories. Therefore, to improve flexibility for programmers, Programmable Read
Only Memory (PROM) is invented. The PROM was invented in 1956 by When
Tsing Chow [1]. The date was 1969 when the first commercial OTP, which is
programmed by anti-fuse based technology, is introduced [3]. In addition, the first
floating gate devices are produced in the 70’s, for example, Texas Instrument
Incorporated invented the floating gate OTP in 1979 [3].
1
In this graduation project, ROM cells designed by using floating gate mosfets. The
goal of the this graduation project is to design a ROM block that only contains
supply pins , write and read pins, a clock input and data input-output pins. Within the
project cell bank is designed to keep 8 bit and have 16 different addresses.
1.2 Motivation
Current trend in memory technology demands cheap, fast, non-volatile and flexible
memory designs. The perfect memory or an ideal memory, is easy and fast program,
can be read fast and is cost effective. Some memory structures can succeed in one or
more of these necessities very well. Although an ideal memory is still a dream, there
are some unique memory structures that are really good.
Today, demand for nonvolatile memories dramatically increasing. As stated in the
article ―Flash Memory Cells—An Overview”, the date was 1997 when it was
predicted that memory market will grow in 2000 [1] .However, today memory devices
are the important part of the integrated circuit (IC) market [2]. In addition, some part
of the IC manufacturers changed their side to share memory market [2]. Nevertheless,
today floating gates are the core of nearly all new nonvolatile memories [7]. In
addition, more than %90 of nonvolatile memory production is based on the Floating
gate technique [8]. Flash memories and therefore floating gate devices plays the most
crucial role in nonvolatile memories [7].
Although, OTP ROM offers more flexibility for the costumers, it has higher cost than
masked ROM. However, this is acceptable cost for OTP. For programming ROMs,
the term ―burn‖ is used since the term was used in original patent.
As stated before Fuse technology uses blown a resistor. As a resistor material polysilicon was usually used in the past but today metal resistors are being used due to
having low resistor than poly-silicon has. Anyway, this technique have some
disadvantages for example using metal as aluminum causes some stability
disadvantages due to having low malting point [4].
2
The devices that have floating gate structures are being more popular day by day.
Because floating gate devices has lots of advantages such as achieving very low
power consumption and being CMOS compatible[9].Even though, floating gate
memories have more complex process, floating gate devices are faster and have
better electromagnetic immunity [9].
Market highlights shows that non volatile memory market is growing [9].
Considering all these advantages and situations, in this graduation project, floating
gate technique is chosen.
1.3 The Floating Gate
1.3.1
Basic Concepts of the Floating Gate
The floating gate is a mosfet that has a floating node at gate terminal. A floating gate
technique uses Fowler-Nordheim theory. Actually, the Fowler – Nordheim (FN)
theory is cold field emission of electrons from a conductor with triangular wave
potential barrier [5]. A generic floating gate NMOS is shown in Figure 1.
Control Gate
Interpoly ox.
Floating Gate
Tunnel ox.
S
D
P- substrate
Figure 1 Cross section of a generic floating gate mosfet
3
The key point in floating gate devices is changing threshold voltage of the mosfet.
For floating gate mosfet, threshold voltage is given by equation 1.
VT
K
QFG
(1)
CCG
K is the constant that depends on doping, gate oxide thickness and substrate and gate
material. Q FG is charge in the floating gate, and CCG is the capacitance between
control gate and floating gate [1].
1.3.2 Tunneling Mechanism
Tunneling is defined as a quantum mechanical process that means a particle such as
electron can pass though into a barrier or forbidden region. In electronic tunneling
means an electron can pass from conduction band to another conduction band
through an insulator region. The energy difference between valance and conduction
band in Si is approximately 1.1eV. The difference of energy in SiO2 is approximately
9eV. When the two elements are put together, the conduction band in SiO2 is 3.25eV
[11]
.
The Fowler-Nordheim tunnel current density is given by equation 2 [11].
J
q3 E 2
exp
8 h b
4(2m)1/ 2
3 qE
3/ 2
(2)
According to the equation 2, the Fowler-Nordheim current density is controlled by
electric field. For programming the nonvolatile devices, a high value of injection
field that is approximately 10MV/cm is necessary [11].
The wave potential probability of an electron is shown in figure 2.
According to the Figure 2, electrons can be found right side of finite potential barrier.
The electron that travels from left to right can be found at left side with higher
probability. In addition, as seen in Figure 2, the electron can change its location to
right side of the barrier by tunneling. However, the amplitude of the probability of
the electron decreases.
4
If the potential barrier is thin, the electron probability amplitude increases according
to Schrödinger equation.
Potantial
Barrier
Figure 2 Quantum tunneling into a barrier
1.3.3 The Challenge of Burning Floating Gate
For writing the information or a data on a floating gate mosfet, the floating gate
mosfet must be exposure to high voltage. However applying high voltages to the
mosfets can cause some problems such as blowing problems. In addition applying
high voltage levels to mosfets, decreases the life of the mosfets. However, within the
project one time programmable read only memory is designed and simulated so the
floating gate mosfet will be programmed only once and therefore high voltage levels
will be applied only once.
5
1.3.4 The Challenge of Determining Logic Values
A Floating gate mosfet may not be good choice to store analog data because the data
depends on electrical charge and the charge that is injected by Fowler-Nordheim
tunneling [6]. Therefore, some addition structure is needed to determine the logic
value. In this graduation project, differential structure is chosen. Hence, there is no
necessity for determining the real value of the analog voltage.
The main idea of the differential structure is looking to the difference and
determining the value. Therefore, there is no problem determining the logic values.
6
2. CIRCUITS
In this project, a One Time Programmable Read Only Memory (OTP ROM) that uses
floating gate technique is designed and simulated. An advance simulation program
which is called Cadence is used for designing and simulating the main parts. The
main parts of OTP ROM are Unit Cell, Output Node Controller, Read Comparator,
Supply Level Translator, Decoder and State Machine. However, output node
controller was not used due to adding state machine.
2.1 Unit Cell
2.1.1 Unit Cell Circuit
The main idea of designing OTP ROM cells predicates on using floating gate PMOS.
If a floating gate mosfet is exposed to high voltage that is approximately 7V to its
drain and source terminals, the floating gate mosfet charges and behaves as a resistor
at normal voltage levels. Applying the high voltage levels to floating gate mosfets is
step of writing procedure. By the memory nature some mosfets needs to be selected
and others does not need to be selected for writing procedure. Hence second mosfet
must be used for selecting the floating gate mosfet. By considering these
specifications a unit cell schematic is designed for OTP. The schematic of a unit cell
is shown in Figure 2.1.
7
CELLSUPPLY
ADRSEL
M0
Floating Gate
PMOS
M1
B<x>
M2
Figure 2.1 Unit Cell
Applying high voltage level (7V) across the drain-source terminals of the floating
gate PMOS (M1) causes the carrier to tunnels to the floating gate hence affectively
shifting the threshold voltage of the PMOS. Level shifted floating gate PMOS
behaves as nearly 30 kΩ. Therefore the drain voltage of M2 is very low voltage while
reading. Hence a differential unit cell that is shown in Figure 2.2 is designed for
solving this problem.
CELLSUPPLY
ADRSEL
M1
M0
FLOATING
GATE PMOS
M3
M2
OUTPUT1
OUTPUT2
B0
M4
B1
M5
Figure 2.2 Differential Unit Cell
8
In order to write to a unit cell, first high supply voltage level should be generated.
Then if the cell should store logic 1, corresponding write transistor should pull the
drain terminal of the floating gate PMOS to ground using B<0> signals. Finally, the
ADRSEL bit should be set to logic 0 to apply high programming voltage level to the
OTP cell. After burning M2 transistor, it behaves as resistor and if M4 is selected by
B0, there is very low voltage will be occur on the drain terminal of the M4. However,
drain voltage of the M5 is the equal to zero because M3 is not burned. Therefore,
voltage level of the drain terminals can be compared.
If the cell store logic 0, B<1> must be selected and B<0> must be reset. In this form,
M3 is going to be burned while M2 not.
2.1.2 Unit Cell Modeling
In the Cadence environment, the floating gate mosfets are modeled for testing as
seen in Figure 2.3 and 2.4.
9
AVDD_CELL
M0
M1
M2
M3
CELL_SEL
CELL_OUTP
CELL_OUTN
R
30kΩ
a)
AVDD_CELL
M1
M0
CELL_SEL
M3
M2
CELL_OUTN
CELL_OUTP
R
30kΩ
b)
Figure 2.3 a) Unit cell which is modeled for Logic 1 b) Unit cell which modeled for
Logic 0
10
OTP_BANKS
AVDD_CELL
AVDD_CELL
CELL_OUTN<7:0>
BANK_SEL<15:0>
CELL_OUTP<7:0>
BANK_SEL<15:0>
OUTP<7:0>
OUTN<7:0>
AVDD
OUTP<7:0>
AVDD
B0<7:0>
B0<7:0>
B1<7:0>
B1<7:0>
AGND
OUTN<7:0>
OTP_DWN_BANKS
AGND
Figure 2.4 Unit Cell with B0<x> and B1<x> select mosfets
OTP_BANKS
AVDD_CELL
AVDD
B0<7:0>
OUTP<7:0>
B1<7:0>
OUTN<7:0>
BANK_SEL<15:0>
AGND
Figure 2.5 Symbol of Cell Bank
A symbol which is seen in Figure 2.5 is used in tests for representing Unit cell.
11
2.2 Output Node Controller
2.2.1
Circuit of Output Node Controller
As stated before, a control mechanism is needed for selecting floating gate mosfets.
B0<x> and B1<x> mosfets are used for control that is needed for reading and writing
procedures. However, the B0<x> and B1<x> mosfets must set or reset depending on
the writing or reading. The conditions are determined for the states and showed in
Table 2.1.
Table 2.1 Truth table of ONC
State
WR
RD
Data
B0
B1
0
0
0
0
1
1
1
0
1
0
1
1
2
1
0
0
0
1
3*
1
1
0
0
0
4
0
0
1
1
1
5
0
1
1
1
1
6
1
0
1
1
0
7*
1
1
1
0
0
State 3 and State 7 are not necessary because write and read procedure cannot be set
at the same time. However these states are used to avoid unwanted situations and B0
and B1 are selected reset position.
12
B0
B0
RD 0
1
0
1
1
1
1
WR
RD 0
1
0
1
1
1
0
WR
Data = 1
B1
RD 0
1
0
1
1
1
0
WR
Data = 0
B1
RD 0
1
0
1
1
1
1
WR
Data = 1
Data = 0
Table 2.2 Karnaugh Maps for B0 and B1
Using the Karnaugh map method, B0 and B1 is found as equation 1 and 2.
B0 = WR + DATARD
(1)
B1=WR+DATARD
(2)
According to logical equation 1 and logical equation 2 a logic circuit occurs as seen
in Figure 2.6.
WR
RD
B0
DATA
B1
Figure 2.6 Logic circuit of ONC
13
However, the logic circuit is redesigned for CMOS by using NOR and NAND gates.
The new design is shown in Figure 2.7.
WR
DATA
B0
RD
B1
DATA
Figure 2.7 ONC which designed by CMOS NOR gates
ONC
AVDD
RD
WR
DATA
B0<7:0>
B1<7:0>
AGND
Figure 8 Symbol of ONC
A symbol which is seen in Figure 2.8 is used in tests for representing Output Node
Controller.
2.2.2
Test Circuit of Output Node Controller
The test circuit that is shown in Figure 2.9 is designed to test ONC.
3.3V
DATA
WR
RD
AGND
AVDD
ONC
0V
AVDD
AVDD
RD
WR
DATA
RD
WR
DATA
AGND
Figure 2.9 Test circuit of ONC
14
AGND
B0<7:0>
B1<7:0>
The logic values of the outputs (B0 and B1) are simulated to test ONC.
2.2.3 Simulation Results of ONC
The simulation results are shown in Figure 2.10 to Figure 2.15. The first one and
second one is about having no read and no write signals. The last one is shows the
outputs of the ONC when the state is reading state. The other is about writing state.
Figure 2.10 Transient analyze of ONC when RD=0 WR=0 DATA=0
15
Figure 2.11 Transient analyze of ONC when RD=0 WR=0 DATA=1
Figure 2.12 Transient analyze of ONC when RD=0 WR=1 DATA=0
16
Figure 2.13 Transient analyze of ONC when RD=0 WR=1 DATA=1
Figure 2.14 Transient analyze of ONC when RD=1 WR=0 DATA=0
17
Figure 2.15 Transient analyze of ONC when RD=1 WR=0 DATA=1
2.1.3. Comments on Simulation Results of ONC
The six different simulations are done. The voltage level of the B0 and B1 depends
on variables are given in the Table 2.3.
Table 2.3 Six different simulations
RD[V]
WR[V]
DATA[V]
B0[V]
B1[V]
SIM 1
0
0
0
3.3
3.3
SIM 2
0
0
3.3
3.3
3.3
SIM 3
0
3.3
0
10n
3.3
SIM 4
0
3.3
3.3
3.3
13n
SIM 5
3.3
0
0
3.3
3.3
SIM 6
3.3
0
3.3
3.3
3.3
18
SIM1 and SIM2 are done when RD and WR equal to logic zero. B0 and B1 is equal
to logic one even though DATA changes. As seen in SIM 3 and SIM 4, B0 stores
same logic value of the DATA’s logic value and B1 keeps the inverse voltage level
of B0.
The voltage levels of BO (at SIM 3) and B1 (at SIM 4) are approximately equal to
10nV. This voltage level is enough for closing NMOS.
In reading procedure simulations that are SIM 5 and SIM 6, B0 and B1 are 3.3V as
expected.
These simulations prove that ONC works clearly.
2.3 Read Comparator
2.3.1
Circuit of Read Comparator
As stated before, after writing data into unit cell, there is a very low voltage that
occurs at the node of output. However, the voltage level of the output is expected
near logic voltage levels. Hence, this low voltage that occurs at the output node
causes a disadvantage for deciding if the output is logic one or logic zero. To solve
this problem a differential pair is used. A device which is called Read Comparator is
needed to compare two outputs of the differential pair and to decide the output
voltage of the unit cell. Therefore three different read comparators are designed for
the OTP ROM.
The schematic of the first design is shown in Figure 2.16. The first design has
differential input stage with folded cascade and output stage.
19
vdd
M14
10/0.35
M3
20/0.35
M15
M4
10/0.35
M2
20/0.35
10/0.35
M5
10/0.35
IB
M11
20/0.35
VOUT
VINP
VINN
M0
M1
30/0.35 30/0.35
M6 10/0.35
M16
M7 10/0.35
M12
20/0.35
10/0.35
R
M8
M17
M18
10/0.35
10/0.35
M9
M13
20/0.35
20/0.35
20/0.35
Figure 2.16 Schematic of first Read Comparator design
The schematic of the second design is shown in Figure 2.17.
vdd
DIS
M8
20µ/0.35µ
M6
1/1
M7
1/1
vdd
SR LATCH
OUT
Q
S
IB
OUTB
Q
R
M4
10/0.35
M5
10/0.35
M9
10/0.35
10/0.35
M10
DIS
VINP
10/0.35
M0
M2
M3
10/0.35
10/0.35
M1
M11
VINN
10/0.35
DIS
10/0.35
Figure 2.17 Second design of Read Comparator
20
C
The schematic of the last design of the read comparator is shown in Figure 2.18.
vdd
DIS
M6
20/0.35
EVA
M5
10/0.35
INPUT
M0
10/0.35
C
M2
OUT
5/0.35
SR LATCH
M3
EVA
INPUTB
5/0.35
M1
10/0.35
S
Q
R
Q
PRE
M4
5/0.35
Figure 2.18 Third design of the Read Comparator
In the third design, to compare the outputs, PRE must be set and after that EVA must
be set. When the EVA is selected outputs are compared.
A symbol which is seen in Figure 2.19 is used in tests for representing Read
Comparator.
READ COMPARATOR
AVDD
EVA
PRE
VINP<7:0>
VINN<7:0>
VOUT<7:0>
DIS
AGND
Figure 2.19 Symbol of read comparator
In this project last design is used.
21
OUT
2.3.2 Test Circuit of Read Comparator
VINP
VINN
PRE
EVA
0V
AVDD
EVA
PRE
VINP
VINN
DIS
AVDD
READ COMPARATOR
AVDD
EVA
PRE
VINP
VINN
VOUT
Figure 2.20 Test circuit of Read Comparator
2.3.4 Simulation Results of RC
The simulation of the Read Comparator is done by using these variables:
VINP: minimum 10nV maximum 100mV
VINN: maximum 100mV minimum 10nV
VINN and VINP are differential inputs of the RC and Q and QB are the outputs of
the SR Latch.
The simulation results are shown in Figure 2.21.
22
100f F
DIS
AGND
AGND
3.3V
DIS
AVDD
AGND
Test circuit of the Read Comparator is shown in Figure 2.20.
Figure 2.21Test result of the RC
2.2.3. Comments on Simulation Results of RC
The differential inputs (VINN and VINP) are coming before Precharge signal. After
Evaluation signal, outputs (Q and QB) are occurring. Q is logic one when VINP is
logic one and Q is logic zero when VINP is logic zero. Hence, RC works clearly.
23
2.4 Bank Select or Supply Level Translator (SLT)
2.4.1
Circuit of the Bank Select
If the state is writing state, cell supply voltage must be approximately 7V. Hence,
unselected addresses behave as selected due to having approximately 3V between
gate and source terminals of the PMOS. To solve this problem a circuit that is called
supply level translator is designed. The schematic of the supply level translator
which is also known as Bank Select is shown in Figure 2.22.
24
CELLSUPPLY
M8
4/0.35
M9
4/0.35
M0
M1
0.4/0.35
0.4/0.35
M10
4/0.35
M12
2/0.35
M13
2/0.35
WRB
100kohm
M2
0.4/0.35
CELLSUPPLY
AVDD
X
M4
0.4/0.35
M3
0.4/0.35
AVDD
M14
4/0.35
M5
0.4/0.35
M15
2/0.35
ADDSEL
M6
2/0.35
M7
2/0.35
Figure 2.22 Schematic of Supply Level Translator (Bank select)
25
A symbol which is seen in Figure 2.23 is used in tests for representing Bank Select.
SLT
CELLSUPPLY
AVDD
ADDSEL<15:0>
X<15:0>
WRB
AGND
Figure 2.23 Symbol of Bank Select
2.4.2
Test Circuit of The Bank Select
WRB
AVDD
ADDSEL
AGND
CELLSUPPLY
Test circuit of the Read Comparator is shown in Figure 2.24.
0V
SLT
CELLSUPPLY
AVDD
ADDSEL<15:0>
X<15:0>
WRB
AGND
Figure 2.24 Test circuit of the Bank Select (Supply Level Translator)
26
2.4.3 Simulation Results of Bank Select
In the first simulation, Cell supply is 3.3V and Vout is equal to 780 mV. The result
of the first simulation is shown in Figure 2.25. This state is tested for reading
procedure when bank is selected.
Second simulation is done to test OUT when the bank is not selected in the read
procedure and is shown in Figure 2.26.
Third simulation (Figure 2.27) and fourth (Figure 2.28) are done to test the bank
select when the state is writing state. In the writing procedure, the voltage level of the
CELLSUPPLY is 7V and OUT must be high enough to close the other banks.
Figure 2.25 Test result of the Bank Select when the bank is selected,-Reading
Procedure- (CELLSUPPLY = 3.3V, ADDSEL= 0V)
27
Figure 2.26 Test result of the Bank Select when the bank is not selected,-Reading
Procedure- (CELLSUPPLY = 3.3V, ADDSEL= 3.3V)
Figure 2.27 Test result of the Bank Select when the bank is selected,-Writing
Procedure- (CELLSUPPLY = 7V, ADDSEL= 0V)
28
Figure 2.28 Test result of the Bank Select when the bank is not selected,-Writing
Procedure- (CELLSUPPLY = 7V, ADDSEL= 3.3V)
2.4.4 Comments of Test Results
As seen in Figure 2.25 and 2.26 voltage level of the Bank Select is enough for
closing or activating the PMOS. The first simulation shows that ouput of the bank
select is approximately 0.6V where cell supply is equal to 3.3V. Second simulation
is about closing PMOS. For closing PMOS logic 1 is needed. As seen in Figure 2.26
the output of the bank select is 3.3V therefore logic one. These two simulations
prove that the bank select can operate regularly when the cell supply is equal to 3.3V.
Next two simulations whose results are seen in Figure 2.27 and figure 2.28 are about
operating when the cell supply is equal to 7V. To close PMOS a logic one is needed
and as seen in Figure 2.28 output is 7V when cell supply is 7V. Therefore bank select
can close the unwanted banks easily.
If a mosfet exposed to high voltages between its terminals for a long time, there can
be some blown problems. Therefore, in writing state, to open a PMOS approximately
29
3.5V is applied to their gate terminals. This voltage is very good for operating safely
when the state is wring state.
2.5 Decoder
2.5.1
Circuit of Decoder
A decoder is designed to select banks. In the writing state only one bank must be
selected while the others are closed. For selecting a bank a logic zero is needed due
to using PMOS. Therefore a nand gate based decoder is good choice.
A logic diagram and a four input NAND gate is shown in figure 2.29.
vdd
M0
M1
M2
M3
E
A
M4
B
M5
C
M6
D
M7
A
B
C
D
a) Schematic of 4-Input NAND
E
b) Symbol of 4-input NAND
30
A
B
C
D
E<0>
E<1>
E<2>
E<3>
E<4>
E<5>
E<6>
E<7>
E<8>
E<9>
E<10>
E<11>
E<12>
E<13>
E<14>
E<15>
c) Logic diagram of 4to16 decoder
Figure 2.29 Schematic of 4to16 decoder
31
A symbol which is seen in Figure 2.30 is used in tests for representing decoder.
DECODER
AVDD
ADR_IN<3:0>
4-16
SEL_OUT<15:0>
AGND
Figure 2.30 Symbol of the 4to16 decoder
2.5.2
Test Circuit of Decoder
AVDD
AGND
Test circuit of the decoder is shown in Figure 2.31.
3.3V
0V
DECODER
ADR_IN<3>
ADR_IN<2>
ADR_IN<1>
ADR_IN<0>
AVDD
AVDD
ADR_IN<3:0>
AGND
4-16
AGND
Figure 2.31 Test circuit of the Decoder
32
SEL_OUT<15:0>
2.5.3
Simulation Results of Decoder
All combination of the inputs (ADR_SEL<3:0> are applied to test circuit and inputs
are shown in figure 2.32.
Figure 2.32 the inputs of the Decoder
The outputs are shown in Figure 2.33 where the inputs are shown as in Figure 2.32.
33
34
Figure 2.33 Outputs (SEL_OUT<15:0>) of the decoder
35
2.5.4
Comments on Test Results
The inputs of the decoder have values between 0 and 15. All combinations of the
inputs are applied to decoder. The first input is 15, the last one is 0 and others are
sorted by decreasing 1. Therefore, outputs are reset in a queue. In a certain time only
one output is equal to logic zero where the others are equal to logic one
This simulation results prove that the decoder works properly.
36
2.6 State Machine
While reading and writing procedures, some signals like PRE and EVA are not
produced in the ROM. They must be applied from output. However, users don’t have
to control the input signals. To solve this problem a state machine is designed in
VERILOG HDL. The state machine controls EVA, PRE, DIS and B<0> B<1>
signals. The logic values of PRE, EVA and DIS are specific for each state of RD and
WR. For writing and reading procedure, desired signals are shown in Figure 2.34.
CLK
RESET
WR
RD
PRE
EVA
DIS
Figure 2.34 Timing diagrams of the signals
A symbol which is seen in Figure 2.35 is used in tests for representing state machine.
State Machine
AVDD
CLK
RD
WR
RESET
DATA<7:0>
PRE
EVA
DIS
B0<7:0>
B1<7:0>
AGND
Figure 2.35 State Machine that is written with Verilog
37
One of the function of the state machine is controlling B0<x> and B1<x> busses.
Therefore, after designing the State machine there is no need for output node
controller.
The state machine is written in a hardware description language that is called
Verilog. The first tests are done by using Xilinx ISE. After uploading the Verilog
codes to Linux machine, a register transfer level (RLT) complier that is called rc is
used to transfer the Verilog codes to Cadence.
2.7 Complete Circuit of the OTP ROM
Finally, all parts of the OTP ROM are get together and a ROM block that is seen in
Figure 2.36 occurs.
A symbol that is shown in Figure 2.37 is created. The OTP ROM block dos not let
the programmer to read and to write at the same time. Therefore data input internally
connected to the output. The data must be applied from output pin when the state is
write state.
38
Figure 2.36
39
OTP ROM
AVDD CELL
AVDD
CLK
RESET
OUT<7:0>
OUTB<7:0>
RD
WR
AGND
Figure 2.37OTP ROM
3. CONCLUSION
In this graduation project, an OTP ROM macro block designed and simulated. From
beginning to end, there were some problems such as determining logic values or
controlling busses. However, by designing new topologies or writing new blocks,
such as state machine, all the problems are solved.
The decoder has 16 different addresses and the bank has 8 bit word length.
Therefore, this OTP ROM can store 16x8 bit.
Finally, a well-operating OTP ROM that is seen in Figure 2.37 is successfully
completed.
40
REFERENCES
[1] P. Pavan, R. BEZ, P. OLIVO,and E. ZANONI, Flash Memory Cells—An
Overview. 1997.
[2] C. F. Yinug, The Rise of the Flash Memory Market. 2007.
[3] Programmable Read Only Memory, Retrieved 10 MAY 2010 from
http://en.wikipedia.org/wiki/Programmable_read-only_memory.
[4] B. Gu at al, Challenges and Future Directions of Laser Fuse Processing in
Memory Repair, 2003.
[5] Richard G. Forbes, Refining the application of Fowler - Nordheim theory,
revised form 1999.
[6] S. M. Sze, Physics of Semiconductor Devices, 2nd Ed. New York.
Wiley, 1981.
[7] Paolo Pavan, L. Larcher and A. Marmiroli, Floating Gate Devices:
Operation and Compact Modeling. Boston: Kluwer Academic Publishers.page 7.
(2004)
[8] P. Cappeletti, C. Golla, P. Olivo, E. Zanoni. Flash Memories. Kluwer
Academic Publ. (1999).
[9] Paolo Pavan, L. Larcher and A. Marmiroli, Floating Gate Devices: Operation
and Compact Modeling. Boston: Kluwer Academic Publishers. page 12. (2004)
[10] C. Y. Chang and S. M. Sze (Eds.), Nonvolatile Memory, John Wiley & Sons,
2000, Chapter 8.
[11] Ashok K. Sharma, Advanced Semiconductor Memories, IEEE Press, 2003, p
340.
41
ADDENDUM
module otp_statemachine(CLK,RESET,WR,RD,DATA,DIS,PRE,EVA,B0,B1);
//====INPUTS================
input CLK,RESET;
input WR,RD;
input[7:0]DATA;
//====OUTPUTS==============
output PRE;
output EVA;
output DIS;
output [7:0]B0;
output [7:0]B1;
reg PRE;
reg EVA;
reg DIS;
reg [7:0]B0;
reg [7:0]B1;
reg [2:0]Counter;
reg Change;
//====PARAMETERS==========
//parameter IDLE=2'b00;
//default added
parameter WRITE=2'b10;
parameter READ=2'b01;
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always @ (posedge CLK or posedge RESET)begin
if (RESET)begin
PRE<=0;
EVA<=0;
DIS<=1;
B0[7:0]<=8'b00000000;
B1[7:0]<=8'b00000000;
Counter<=0;
Change<=0;
end
else begin
case ({WR,RD})
default:
begin
PRE<=0;
EVA<=0;
DIS<=1;
B0[7:0]<=8'b00000000;
B1[7:0]<=8'b00000000;
Counter<=0;
Change<=0;
end
READ:
begin
Counter <= Counter + 1;
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DIS<=0;
B0[7:0]<=8'b11111111;
B1[7:0]<=8'b11111111;
if (Change == 0)begin
//PRE is logic one here
PRE<=1;
if (Counter ==3) begin
Change <=1;
end
else begin
Change <=0;
end
end
else begin
//Change is one here
PRE<=0;
if (PRE ==0)begin
// to wait one clk cycle
if (Counter == 3)begin
Change <= 1;
//for a reading loop
end
else begin
EVA <= 1;
end
end
else begin
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EVA<=0;
end
end
end
WRITE:begin
PRE<=0;
EVA<=0;
DIS<=1;
if (DATA[0]==0)begin
//DATA[0]
B0[0]<=0;
B1[0]<=1;
end
else begin
B0[0]<=1;
B1[0]<=0;
end
if (DATA[1]==0)begin
//DATA[1]
B0[1]<=0;
B1[1]<=1;
end
else begin
B0[1]<=1;
B1[1]<=0;
end
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if (DATA[2]==0)begin
//DATA[2]
B0[2]<=0;
B1[2]<=1;
end
else begin
B0[2]<=1;
B1[2]<=0;
end
if (DATA[3]==0)begin
//DATA[3]
B0[3]<=0;
B1[3]<=1;
end
else begin
B0[3]<=1;
B1[3]<=0;
end
if (DATA[4]==0)begin
//DATA[4]
B0[4]<=0;
B1[4]<=1;
end
else begin
B0[4]<=1;
B1[4]<=0;
46
end
if (DATA[5]==0)begin
//DATA[5]
B0[5]<=0;
B1[5]<=1;
end
else begin
B0[5]<=1;
B1[5]<=0;
end
if (DATA[6]==0)begin
//DATA[6]
B0[6]<=0;
B1[6]<=1;
end
else begin
B0[6]<=1;
B1[6]<=0;
end
if (DATA[7]==0)begin
//DATA[7]
B0[7]<=0;
B1[7]<=1;
end
else begin
B0[7]<=1;
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B1[7]<=0;
end
end
endcase
end
end
endmodule
48
BIOGRAPHY
Emrah YASAN was born in KONYA, TURKEY in 1987. He graduated from
Meram Anadolu Lisesi in 2005 and he joined Istanbul Technical University,
Electronic Engineering Programme in the same year. His research interests cover
microelectronics.
49