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Transcript
Project Draft 1: High Sensitivity, Very Low Drift Temperature Sensor With Digitized Output
Through their constant miniaturization and increasing accuracy, temperature sensors are starting to be
used in an increasing number of unique medical and environmental applications. The integration of RFID
tags with temperature sensors provides wireless temperature sensing capabilities, which is useful in, for
example, monitoring the temperature of perishable food [1]. However the challenge with such portability
arises in maintaining accuracy despite low power constraints. Accurate wireless body temperature
monitoring has been successfully achieved, but only in a limited range, from 35°C to 45°C [2]. A wider
range with an accuracy of ±0.1°C would be desirable in order to extend the usefulness of the RFID based
temperature sensor to environmental applications in order to supplement humidity and pressure data with
temperature measurements [3]. Thus, the development of an accurate temperature sensor with a wide
sensing range is important because it would not only enable its use in the previously mentioned
applications, but can also "open up new applications in the medical, industrial, automotive, and consumer
fields" [4].
A proposed top level system block diagram for the design of the temperature sensor is shown below in
Figure 1.
Figure 1. System level block diagram for proposed temperature sensor integrated circuit.
All of the components for the proposed temperature sensor will be entirely on-chip except for the clock
signal used to drive the 14-bit ADC. The clock signal, for example, may be received from a crystal
oscillator located on the same PCB. A temperature independent band-gap reference (BGR) of 1.2 V will
be used for the ADC and may also be used for the temperature sensor and the auto-zeroing operational
amplifier (op-amp) configurations. Since the device will be used in extreme temperature conditions, a
BGR is necessary to ensure stable circuit operation. The temperature sensor will generate a proportional
to absolute temperature (PTAT) voltage output. The PTAT voltage output will first be fed through an
auto-zeroing op-amp configuration. This particular op-amp configuration enforces stability to eliminate
errors associated with temperature drift and with the offset voltages associated with the op-amps
themselves. Finally, the output of the op-amp configuration is used by the ADC to generate a digital
output. A special second order ADC is utilized to achieve high accuracy and low power consumption.
A standard BGR will be used to create a temperature independent voltage reference off of which some or
all of the other blocks will operate. The input to the BGR is the supply voltage and the output is the 1.2 V
reference voltage.
The temperature sensing circuit, adopted from Makinawa, will have two identical substrate PNP bipolar
transistors with a collector current ratio set to 1:p, due to a PMOS current mirror load [4]. As a result, the
∆VEB of the PNP transistors equals (kT/q)*ln(p), which is a PTAT voltage since it is linearly proportional
to the temperature. The temperature sensing circuit described can be seen in Figure 2. The input for the
temperature sensing circuit is a simple bias voltage for the PMOS current mirror and the output is a PTAT
voltage or current [4].
Figure 2. Basic schematic of temperature sensing circuit [4].
The op-amp that will be used with the temperature sensing circuit to reduce the temperature drift of the
PTAT voltage or current will be an auto-zeroing operational amplifier. This type of operational amplifier
will be used since the offset voltage of the amplifier can be reduced by a factor of up to 500 [5]. Figure 3
shows a diagram of an auto-zeroing op-amp configuration that can be used to nullify the effects of the
offset voltage. Essentially, a nulling amplifier is inserted along with the wideband amplifier so that the
offset calibration path is in parallel with the signal path. With a clock signal, the circuit will be in two
phases in a clock cycle: the auto-zero phase and the signal amplification phase [5].
Figure 3. Diagram of the auto-zeroing op-amp configuration [5].
The input of the block includes bias voltages and currents, the PTAT voltage, and a clock signal for the
switches if an on-chip oscillator cannot be implemented. The output of the op-amp is an output voltage
with a low offset.
The proposed design of the ADC uses the zoom-ADC topology implemented by Makinawa. Since
temperature sensing applications do not generally require high-speed performance, the disadvantage of
increased computational time from the multiple steps employed by the zoom-ADC is trivial compared to
the high resolution and accuracy that the topology offers. The coarse stage of the ADC will use a 5-bit
SAR to determine the integer value of the VBE/∆VBE ratio (these values are input from the temperature
sensor), as seen in Figure 4a [6]. The fine stage will then determine the fractional component of the ratio
and convert it into a 9-bit digital signal. This stage is implemented with a Σ∆-ADC, represented in Figure
4b. This stage is designed to be second-order due to the lower power consumption of two low-gain
integrators compared to the single, high-gain integrator of a first-order design. The op-amps used for the
integrators in this stage should be designed for low power consumption and relatively high gain, which
can be provided by a telescopic op-amp [6].
Figure 4. Block diagrams of the coarse (a) and fine (b) ADC topologies [6].
The proposed system will be implemented with the 0.5-µm standard CMOS process, which will use a
supply voltage of 3 V. Many current temperature sensing circuits function in the 1-2 V supply range and
can therefore achieve low power consumption; however, the proposed design will aim for about 800 µW
of power consumption as a reasonable benchmark to achieve the desired resolution and accuracy with a 3
V supply. For this low power design, it would be practical to implement the ADC with 14 bits, which
provides enough resolution within the range of operating temperatures and does not require a large supply
voltage. A benchmarking table that provides a comparison between our proposed design and the state of
the art design is shown in Table 1.
Table 1. Comparison of State-of-the-Art and Proposed Specifications
State-of-the-Art Design [4]
Proposed Design
14
~13
Number of Bits
.1 °C
.022 °C
Resolution
800 µW
~300 µW
Power Consumption
-40° - 125°C
-55° - 125°C
Temperature Range
±.2 °C
±.15 °C
Accuracy
3V
1.5 V – 2 V
Supply Voltage
Table 2 provides a proposed list of tasks that need to be accomplished and the group members responsible
for them.
Table 2. Proposed Delegation of Tasks to Group Members
Task
Draft 2
System Level and Circuit Simulation
-Voltage Reference
-Temperature Sensor
-Auto-Zeroing Op-Amp Configuration
-Zoom-ADC
Design Review
Layout (Zoom-ADC)
Post Layout Simulation (Zoom-ADC)
Final Presentation
Final Paper
Team Member(s) Responsible
All
Samrat
Ankur
Jeff
All
All
Samrat, Ankur
Jeff
All
All
References:
[1] M. Law, A. Bermark, and H. C. Luong, “A sub- µW embedded temperature sensor for RFID food
monitoring application,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1246–1255, Dec. 2010.
[2] A. Vaz et al., “Full passive UHF tag with a temperature sensor suitable for human body temperature
monitoring,” IEEE Trans. Circuits Syst. II, vol. 57, no. 2, pp. 95–99, Feb. 2010.
[3] H. Shen, L. Li, and Y. Zhou, “Fully integrated passive UHF RFID tag with temperature sensor for
environment monitoring,” in Proc. 7th Int. Conf. ASIC, Oct. 2007, pp. 360–363.
[4] Souri, K.; Youngcheol Chae; Makinwa, K.A.A., "A CMOS Temperature Sensor With a VoltageCalibrated Inaccuracy of ±0.15°C (3σ) From 55°C to 125°C," IEEE J. Solid-State Circuits, vol.48, no.1,
pp.292-301, Jan. 2013
[5] Kugelstadt, Thomas, “Auto-zero amplifiers ease the design of high-precision circuits,” Amplifiers: Op
Amps, Texas Instruments Inc, Texas, Tech. Rep, 2005.
[6] K. Souri and K. A. A. Makinwa, “A 0.12 mm 7.4 W micropower temperature sensor with an
inaccuracy of ±0.2°C from -30°C to 125°C,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1693–1700,
Jul. 2011.