Download Classification Of Output Stages

Microelectronic Circuits
Output Stages
Ching-Yuan Yang
National Chung-Hsing University
Department of Electrical Engineering
Outline
z Classification of Output Stages
z Class A Output Stage
z Class B Output Stage
z Class AB Output Stage
z Biasing the Class AB Circuit
z Variations on the Class AB Configuration
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Classification Of Output Stages
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Class A Stage
The class A stage is biased at a current IC greater than the amplitude of the
signal current, Iˆc .
The transistor in a class A stage conducts for the entire cycle of the input signal;
that is, the conduction angle is 360o.
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Class B Stage
The class B stage is biased at zero dc current.
The transistor in a class B stage conducts for only half of the cycle of the input
sine wave, resulting in a conduction angle of 180o.
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Class AB Stage
An intermediate class between A and B, named class AB, involves biasing the
transistor at a nonzero dc current much smaller than the peak current of the
sine-wave signal.
The transistor in a class AB stage conducts for a interval slightly greater than
half a cycle. The resulting conduction angle is greater than 180o but much less
than 360o.
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Class C Stage
The transistor in a class C stage conducts for an interval shorter than that of a
half cycle; that is, the conduction angle is less than 180o.
Class C amplifiers are usually employed for radio-frequency (RF) power
amplification (required, for example, in mobile phones and TV transmitters).
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Class A Output Stage
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Transfer Characteristic
Because of its low output resistance, the emitter follower is the most popular
class A output stage.
An emitter follower (Q1) biased with a constant current I supplied by transistor Q2:
† Since iE1 = I + iL, the bias current I must be
greater than the largest negative load current;
otherwise, Q1 cuts off and class A operation will
no longer be maintained.
† The transfer characteristic of the emitter follower:
vO = vI − vBE1
where vBE1 depends on the emitter current iE1
and thus on the load current iL.
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Transfer characteristic of the emitter follower:
vO = vI − vBE1
‡ The linear characteristic is obtain by neglecting the change in vBE1 with iL.
‡ The maximum positive output is determined by the saturation of Q1:
vO max = VCC − VCE1sat
‡ In the negative direction, the limit of the linear region is determined either by Q1
turning off or by Q2 saturating, depending on the values of I and RL.
n Q1 turning off : vO min = − IRL
o Q2 saturating : vO min = −VCC + VCE 2sat
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(the absolutely lowest output voltage)
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‡ Biasing current:
The bias current I is greater than the magnitude of the corresponding
load current. ( I ≥ iL )
I ≥
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− VCC + VCE 2sat
RL
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Signal Waveforms
(Neglect vCEsat ) Consider that maximum signal waveforms are under the condition I = VCC /RL.
vCE1 = VCC − vO
The instantaneous power dissipation in Q1:
PD1 = vCE1iC1
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Power Dissipation
‡ Maximum instantaneous power dissipation in Q1 = VCC I. (vO = 0).
‡ The power dissipation in Q1 depends on the value of RL.
If RL = ∞, then
~ ic1 = I, constant.
~ The maximum power dissipation will occur when vO = −VCC.
Ö PD1 = 2VCC I.
~ The average power dissipation in Q1 is VCC I.
If RL = 0, then
~ A very large current may flow through Q1. It raises the junction
temperature beyond the specified maximum, causing Q1 to burn up.
~ Need short-circuit protection.
‡ The maximum instantaneous power dissipation in Q2 is 2VCC I when vO
= VCC . A more significant quantity for design purpose is the average
power dissipation in Q2, which is VCC .
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Power Conversion Efficiency
‡ Power-conversion efficiency
η≡
Signal power delivered to load (PL )
× 100%
dc power supplied to output circuit (PS )
‡ Average load power
∧
1 VO2
PL =
2 RL
‡ Total average supply power:
PS = 2VCC I
n Since the current in Q2 is constant (I ), the power drawn from the
negative supply is VCC I .
o The average current in Q1 is equal to I, and thus the average power
drawn from the positive supply is VCC I .
Thus, the total average supply power is PS = 2VCC I .
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Determine power-conversion efficiency of the class A output stage :
η=
1 VˆO2
1 ⎛ Vˆ ⎞⎛ Vˆ ⎞
= ⎜⎜ O ⎟⎟⎜⎜ O ⎟⎟
4 IRLVCC 4 ⎝ IRL ⎠⎝ VCC ⎠
‡ Small signal, i.e., VˆO is small,
~ η → 0.
~ static power consumption 2VCC I even no excitation.
‡ Since VˆO ≤ VCC and VˆO ≤ IRL , maximum efficiency is obtained when
VˆO = VCC = IRL . ∴
ηmax = 25%
‡ In practice the output voltage is limited to lower values in order to avoid
transistor saturation and associated nonlinear distortion.
Ö The efficiency achieved is usually in the 10% to 20% range.
z Class A operation is a poor choice for power amplification.
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Class B Output Stage
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Output Stages
z Ideal output stages
Ž Supply external load current
Ž Low output impedance
Ž Large output swing ≈ VCC − VEE (ideally)
z Commonly used complementary emitter follower
Ž Each transistor is on for only half the time.
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Circuit Operation
Class B output stage consists of a complementary pair of transistors connected
in such a way that both conduct simultaneously.
n vI = 0 , Ö QP and QN are cut off and vO = 0 .
o vI > 0.5V , Ö QP is cut off ; QN turns on and
acts as an emitter follower.
vO = vI − vBEN
and QN supplies the load current.
p vI < −0.5V , Ö QN is cut off ; QP conducts
and operates as an emitter follower.
vO = vI + vEBP
and QP supplies the load current.
Operation in push-pull fashion:
z The transistors in class B stage are biased at zero current and conduct only when the
input signal is present.
z QN pushes (sources) current into the load when vI is positive, and QP pulls (sinks)
current from the load when vI is negative.
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Transfer Characteristic
There exists an range of vI centered around zero where both transistors are
cut off and vO is zero. This dead band results in the crossover distortion.
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Illustrating how the dead band in the class B transfer characteristic results in
crossover distortion.
The effect of crossover distortion will be pronounced when the amplitude of
the input signal is small. Crossover distortion in audio power amplifiers gives
rise to unpleasant sounds.
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Power Conversion Efficiency
We neglect the crossover distortion and consider the case of an output sinusoid
of peak amplitude Vˆo .
1 Vˆo2
‡ Average load power PL =
2 RL
‡ Total supply power
n The peak amplitude of current draw from supply: Vˆo R L
o The average current draw from supply: Vˆo πR L
The average power drawn from each of the two power supplies:
1 Vˆo
PS + = PS − =
V
π R L CC
2 Vˆo
The total supply power PS =
VCC
R
π
L
π Vˆo
‡ Efficiency η =
(14.15)
4 VCC
ηmax =
π
= 78.5% when
Vˆo = VCC − VCEsat ≈ VCC
4
2
1 VCC
‡ Maximum average power available PL max =
2 RL
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Power Dissipation
Unlike the class A stage, which dissipates maximum power under quiescent
conditions (vO = 0), the quiescent power dissipation of the class B stage is zero.
‡ Average power dissipation
2 Vˆo
1 Vˆo2
PD = PS − PL =
V −
π R L CC 2 R L
⎛ ∂P
⎞
‡ Maximum average power dissipation ⎜⎜ ˆD = 0 ⎟⎟
⎝ ∂Vo
⎠
2
2V
2
PD max = 2 CC when Vˆo P
= VCC
D max
π RL
π
∴ PDN max = PDP max
2
VCC
= 2
π RL
By Eq. (14.15), at the point of max. power dissipation the efficient η =
50%.
1 Vˆo2
‡ Average load power PL =
2 RL
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Power dissipation of the class B output stage versus amplitude of the output sinusoid.
PD =
2 Vˆo
1 Vˆo2
VCC −
2 RL
π RL
Increasing Vˆo beyond 2VCC /π decreases the power dissipated in the class B stage
while increasing the load power.
The price paid is an increase in nonlinear distortion as a result of approaching the
saturation region of operation of QP and QN. Transistor saturation flattens the peaks of
the output sine waveform.
‡ This type of distortion cannot be significantly reduced by the application of
negative feedback.
‡ The transistor saturation should be avoided in applications requiring low THD.
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Example 9.1 Class B output stage design
The class B output stage deliver an average power of 20W to an 8-Ω load. Select the
power supply such that VCC is about 5V greater than the peak output voltage. This avoids
transistor saturation and the associated nonlinear distortion, and allows for including shortcircuit protection circuitry. Determine the supply voltage required, the peak current drawn
from each supply, the total supply power, and the power-conversion efficiency. Also
determine the maximum power that each transistor must be able to dissipate safely.
Solution
1 Vˆo2
2 RL
Vˆo = 2PL R L = 2 × 20 × 8 = 18V
17.9
Vˆ
= 2.24A
o The peak current drawn from each supply Iˆo = o =
8
RL
1 Vˆo
1
VCC = × 2.24 × 23 = 16.4W
p The average power drawn from each supply PS + = PS − =
π RL
π
q Total supply power = PS+ + PS− = 32.8W
n Determine VCC : PL =
Ö
20
PL
=
= 61%
PS 32.8
s The maximum power dissipated in each transistor
r The power-conversion efficiency η =
PDN max = PDP max =
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(23)2
VCC
= 2
= 6.7W
2
π RL π × 8
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Distortion in the Class B Push-Pull Stage
z Harmonic distortion
‡ For matched devices QN & QP
‡ iN and iP are identical except shifted
in phase by 180o
iN
iN = I c + B 0 + B1 cos ωt + B 2 cos 2ωt + B 3 cos 3ωt + "
iP
iP (ωt ) = iN (ωt + π )
iP = I c + B 0 − B1 cos ωt + B 2 cos 2ωt − B 3 cos 3ωt + "
i L = iN − iP = 2(B1 cos ωt + B 3 cos 3ωt + ")
Even-order harmonic distortions have been eliminated.
If I -Vs of QN & QP are not identical, then even-order harmonic is expected.
z Crossover distortion: has been discussed before.
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Reducing Crossover Distortion
Class B circuit with an op amp connected in a negative-feedback loop to reduce
crossover distortion
z The ±0.7V dead band is reduced to ±0.7/A0 volts, where A0 is the dc gain
of the op amp.
z Slew-rate limiting of the op amp.
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Single-Supply Operation
Class B output stage operated with a single power supply
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Class AB Output Stage
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Class AB Output Stage
z Crossover distortion can be virtually eliminated by biasing the complementary
output transistors at a small, non-zero current.
z A bias voltage VBB is applied between the bases of QN and QP , giving rise to
a bias current
iN = iP = I Q = I S eVBB /2VT (Assuming matched devices)
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Circuit Operation
n v BEN + v EBP = VBB
⎛i ⎞
⎛i ⎞
⎛i ⎞
⇒ VT ln⎜⎜ N ⎟⎟ + VT ln⎜⎜ P ⎟⎟ = 2VT ln⎜⎜ Q ⎟⎟
⎝ IS ⎠
⎝ IS ⎠
⎝ IS ⎠
⇒ iN iP = iQ2
As iN increases, iP decreases by the same ratio while the product remains constant.
o iN = iP + iL
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⇒ iN2 − i L iN − I Q2 = 0
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Output resistance
Determine the small-signal output resistance of the class AB circuit
Rout = reN reP
where reN and reP are the small-signal emitter
resistances of QN and QP , respectively.
reN =
VT
iN
⇒ Rout =
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and
reP =
VT
iP
VT VT
VT
=
iN iP
iP + iN
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Biasing The Class AB Circuit
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Biasing Using Diodes
Class AB output stage utilizing diodes for biasing. If the junction area of the
output devices, QN and QP , is n times that of the biasing devices D1 and D2, a
quiescent current IQ = nIbias flows in the output devices.
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Example 14.2 Class AB output stage design
VCC = 15V, RL = 100Ω, and the output is sinusoidal with a maximum amplitude of 10V.
Let QN and QP be matched with IS = 10−13A and β = 50. Assume the biasing diodes have
one-third the junction area of the output devices. Find the value of Ibias that guarantees a
minimum of 1mA through the diode at all times. Determine the quiescent current and the
quiescent power dissipation in the output transistors (i.e., at vO = 0 ). Also find VBB for vO
= 0 , +10V, and −10V.
n The maximum current through QN :
iLmax = 10V/0.1k Ω =100mA
The maximum base current in QN is 2mA.
o To maintain a min. of 1mA through the diodes, we
select Ibias = 3mA.
Ö A quiescent current of 9mA through QN and QP .
Quiescent power dissipation
PDQ = 2×15×9 = 270mW
p For vO = 0 , IB,Q1 = 9/51 = 0.18mA.
∴ ID = ID1,D2 = 3 − 0.18 = 2.82mA
−13
q Since the diodes have I S = 13 × 10 , then
2.82mA
I
VBB = 2 × VT ln D = 2 × 0.025 × ln
= 1.26V
IS
IS
r vO = +10V Ö ID ≈ 1mA Ö VBB = 1.21V
s vO = −10V Ö ID ≈ 3mA Ö VBB ≈ 1.26V
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Biasing using the VBE multiplier
Find VBB :
IR =
VBE1
R1
⎛
R ⎞
VBB = I R (R1 + R2 ) = VBE1 ⎜⎜1 + 2 ⎟⎟
R1 ⎠
⎝
Determine VBE1 :
I C1 = I bias − I R
⎛I ⎞
VBE1 = VT ln⎜⎜ C1 ⎟⎟
⎝ I S1 ⎠
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A discrete-circuit class AB output stage with a potentiometer used in the VBE
multiplier. The potentiometer is adjusted to yield the desired value of quiescent
current in QN and QP.
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Variations On The Class AB Configuration
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Use of Input Emitter Followers
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z
High input resistance
z
Quiescent current in Q3 and Q4 is equal
to that in Q1 and Q2 if RL = ∞ and R3 =
R 4 ≈ 0.
z
R3 and R4 are small and are included to
guard against the possibility of thermal
runaway due to temperature differences
between the input and output – stage
transistor.
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Use of Compound Devices
The Darlington configuration
1.
2.
3.
4.
increase current gain
reduce base current drive
Equivalent VBE(eq.) = 2VBE
can be used for both NPN
transistors and PNP transistors
1.
used to improve PNP
configuration
Q1 is usually a lateral PNP
having low β (≈ 5−10)
The compound-pnp configuration
2
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A class AB output stage utilizing a Darlington npn and a compound pnp.
Biasing is obtained using a VBE multiplier.
• Bias is obtained using a VBE multiplier.
• VBE multiplier is required to provide 3VBE.
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Short-Circuit Protection
A class AB output stage is equipped with protection against the effect of shortcircuiting the output while the stage is sourcing current.
n A large current that flows through Q1 in the
event of a short circuit will develop a
voltage drop across RE1 of sufficient value
to turn Q5 on.
o The collector of Q5 will then conduct most
of the current Ibias , robbing Q1 of its base
drive.
p The current through Q1 will thus be reduced
to a safe operating level.
iL  Ö VRE1  Ö IC5  Ö IB1 ‚ Ö IC1 ‚
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Thermal Shutdown
Thermal shutdown circuit
Transistor Q2 is normally off.
n As the chip temperature rises, a combination of
positive temperature coefficient of zener diode Z1
and the negative temperature coefficient of VBE1
causes the voltage at the emitter of Q1 to rise.
o This in turn raises the voltage at the base of Q2 to
the point at which Q2 turns on.
T  Ö VZ1 , VBE ‚ Ö VR2  Ö IC2 
¨ Q2 absorbs bias current of OPAMP
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Homework
z Problem 2, 11, 16, 19, 33
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