Download TCAD Modeling of Stress Impact on Performance and

TCAD Modeling of Stress Impact
on Performance and Reliability
Xiaopeng Xu
TCAD R&D, Synopsys
March 16, 2010
SEMATECH Workshop on Stress Management for 3D ICs using Through Silicon Vias
1
Outline
•
Introduction
–
–
•
TCAD stress modeling
–
–
–
•
Modeling requirements
Multi-scale process simulation with layout
Performance and reliability analysis
Stress management with TCAD
–
–
•
Stress in device, interconnect and TSV stack
Stress impact on performance and reliability
Device stress engineering
Design and technology exploration
Summary
2
Ubiquitous Mechanical Stress
Mechanical
Failure and
Reliability in
Stressed 3D
Structures
Low-k
G ate
S pacer
C ap la yer
Silicon die 2
Si3N4
μ-bump
Cu
S TI
SiG e S/D
Low-k
Z
TSV
Die 1
SiO2
X
001/110
Silicon
Y
Performance
Modulation in
Stressed
Transistors
Bump
Package Substrate
™ Typical stress source:
o
o
o
o
Thermal mismatch due to temperature ramps
Lattice mismatch from epitaxy grain growth
Intrinsic stress due to material bonding
Force rebalance after etching, deposition, thinning, bumping, and stacking
™ Stress impact:
o Band structure change induces device performance variation
o Mechanical deformation leads to damage and reliability degradation
3
Stress Impact on Device Performance
Far
Close
Compressive ESL
simulations
K.V.Loiko et al. 2006
AMAT/IMEC/SNPS 2006
4
Stress Impact on BEOL Reliability
•
3D structure from
ƒ
Layout
ƒ Process
•
•
Distinct materials
Non-uniform stress
Cracking in
Dielectrics
Voiding in Copper
De-lamination along
Low k Interface
J. McPherson, TI, 2006
K. Ueno, NEC 2005
T. Huang, TSMC, 2006
5
TSV Mechanical Stress Related Concerns
New Stress Sources
•
•
•
New thermal mismatch stresses
Copper grain growth stress in TSV
New material interactions
Stress Concern Examples
TSV extrusion and de-lamination
•
Manufacturability
– Effect of thin die warping
– Effect of die stacking
- P. Ho, RTI 3D Symposium 2009
•
Reliability
– Cracking around TSV
– Layer de-bonding and de-lamination
– TSV deformation and voiding
•
Performance (mobility) variability
– Stress relaxation due to thinning
– TSV and u-Bump proximity effects
Performance shifting after wafer thinning - QCT/IMEC, DATE 2009
6
Outline
•
Introduction
–
–
•
TCAD stress modeling
–
–
–
•
Modeling requirements
Multi-scale process simulation with layout
Performance and reliability analysis
Stress management with TCAD
–
–
•
Stress in device, interconnect and TSV stack
Stress impact on performance and reliability
Device stress engineering
Design and technology exploration
Summary
7
Stress Modeling Requirements
• Structure generation
– Fabrication process: e.g. deposition, etching
– Design layout
• Stress analysis
– Stress source
• Thermal mismatch from process flow
• Intrinsic bonding from material formation
• External loading from stacking and packaging
– Stress evolution
• Different stress laws for various materials
• Models for stress effect
– Stress-to-mobility model for performance
– Stress-to-damage model for reliability
• Design and technology exploration
– Design variables: size, pitch, KOZ, pattern, rules
– Technology variables: material, insulation, wafer thinning
8
TCAD TSV 3D Simulation Flow
Process Info
Layout Info
Deposition Material=Oxide thickness=0.3
Etch mask=Metal_2 Material=Oxide thickness=0.3
Process Simulation
Finite Element Analysis
Mobility
Variation
Global
Model
3D Structures
Solution Fields
Reliability Analyses
Mobility Variations
Reliability
Effective
Stress
Material Property
Database
Submodel 1
Submodel 3
t=400um
Die Thinning
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Submodel 2
t=20um
TSV Process/Stress Simulation Example
FEOL
TSV
• FEOL
• TSV
• BEOL
BEOL
Thinning
μ-Bump
Stacking
• Stacking
• μ-bump
• Thinning
• Backside
TSV:
• deep etch
• oxidize
• plate and
fill (cu)
Backside
Die 2
μ-bump
Die 1
Die 1
TSV
Silicon
BEOL
Hydrostatic Stress
before and after
Die 1 and 2 Stacking
Die 2
Die 2
MPa
Die 1
Die 1
High TSV Stress
10
• Process simulation for TSV
and stacking is required to
track the stress evolution.
• Same stress results can be
used to analyze reliability
and mobility change.
Stress Impact on Electrons and Holes
Stressed
ml
mt
Electron Band Change under Stress
Ec[001]
•
Ec[010]
Ec[100]
m t < ml
[001] valley lowered and [010]
[100] valley raised with stress
Carrier repopulation into lower Δ2
valley with small transport mass
along <110>
•
Δ2
Δ4
Hole Band Change under Stress
Relaxed
Stressed
•
•
11
<110> mass decreased with
compressive stress
Carrier repopulation into valley
with smaller <110> mass
Stress Induced Voiding and Cracking
Stress Migration Model for Metal Voiding
K. Ueno, NEC 2005
normal
1
0.5
0
-0.5
-1
-1
-1.5
-1
0
1
2
3
Δn/δn
12
6
7
-1.5
-3
-2
-1
0
Δt/δt
1
2
3
De-bonding
M3
M2
Oxide
Accumulated vacancy density in metal
5
M4
Oxide
Unit: % (normalized to
initial concentration)
4
X. Xu and A. Needleman, 1994, JMPS
Low k
Copper
0
-0.5
Barrier
tangential
1
0.5
-Tn/σmax
T.C. Huang, et al., IITC 2003
1.5
1.5
2
-T t/τmax
1 ∂C 1
∇C=
−
∇ ⋅ ∇σ H
D ∂t kT
Cohesive Zone Model
J. McPherson, TI, 2006
Silicon Mobility Variation around TSV
001 Wafer, 110 Flat
Orientation
TSV Array
Mobility Variation (%)
30
n‐Si, Cu Via
25
p‐Si, Cu Via
20
15
10
5
0
‐5
0
Si
Cu
Layout: 5/25
4
6
8
10
10
5
0
‐5
‐10
‐15
‐20
n‐Si, Cu Via
‐25
p‐Si, Cu Via
‐30
0
2
4
6
8
10
Distance along x‐axis (micron)
13
12
Distance along y‐axis (micron)
Mobility Variation (%)
Barrier
2
12
Thermal Stress Induced TSV Pop-up
Expansion
Contraction
ΔT > 0
ΔT < 0
Szx (MPa)
Large shear stress at TSV-silicon interface leads to de-bonding
14
Sub-modeling
Barrier
(Oxide)
TSV
TSV
Epoxy
Landing
Pad
r
a
e
m
S
Oxide
Low-k
Landing
Pad
Nitride
Si
Metal
Lines
z
y
x
Global TSV structure and
submodeling
15
Landing pad and metal lines in
the submodel (back view)
Outline
•
Introduction
–
–
•
TCAD stress modeling
–
–
–
•
Modeling requirements
Multi-scale process simulation with layout
Performance and reliability analysis
Stress management with TCAD
–
–
•
Stress in device, interconnect and TSV stack
Stress impact on performance and reliability
Device stress engineering
Design and technology exploration
Summary
16
Stress Engineered Transistors
20nm nMOS
20nm pMOS
• Tensile CESL
• Recessed SiC S/D
• Geometry optimization
• Compressive CESL
• Elevated SiGe S/D
• Geometry optimization
SNPS @ ECS 2005
17
001/110
Keep Out Zone around TSV
001 Wafer, 110 Flat Orientation
Si/STI/TSV
Layout:
5/30
Active:
0.5/1.0
STI:
0.5
KOZ: Keep Out Zone
KOZ
Sxx in Silicon (MPa)
18
P-Si Mobility Variation (%)
TSV Diameter Impact on Performance
001 Wafer, 110 Flat Orientation
TSV Diameter = 5 um
Mobility Variation (%)
40
TSV Diameter = 10 um
~38% higher normal stress
Sxx (MPa)
p‐Si, Cu Via
35
d=10 um
30
d=5 um
25
20
15
10
5
0
0
2
4
6
8
10
12
Distance along y‐axis (micron)
Larger TSV diameter leads to larger mobility change in silicon
19
TSV Diameter Impact on Reliability
~112% more max displacement
Expansion
ΔT > 0
D = 10 um
D = 5 um
Szx (MPa)
Szx (MPa)
Larger TSV diameter leads to larger deformation and shear stress
20
Insulation Material Impact on Performance
001 Wafer, 110 Flat Orientation
Mobility Variation (%)
30
Oxide
> 80% modulus reduction
~50% less normal stress
Low k
25
Oxide
20
p‐Si, Cu Via
15
10
5
Sxx (MPa)
0
0
2
4
6
8
10
12
Distance along y‐axis (micron)
Low k
Low k insulation reduces mobility variation in silicon
21
Insulation Material Impact on Reliability
~70% more displacement
ΔT > 0
Oxide insulation
Low k insulation
Low k insulation provides less resistance to Cu extrusion
22
TSV Material Effects
Cu
Si
Cu
W
Si
Cu
Copper TSV
Tungsten TSV
Effective Stress
Tungsten has less mismatch with silicon but more with copper
23
Summary
• Large mechanical stresses are present in
device, interconnect, and TSV stack.
• Complex stress interactions impact both
performance and reliability.
• 3D TCAD process simulation of stress
evolution provides valuable insights for tech
tuning and stress management.
• Studies on stress engineering, performance
and reliability trade-off are carried out for
design and technology explorations.
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