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DAC7800
DAC7801
DAC7802
®
Dual Monolithic CMOS 12-Bit Multiplying
DIGITAL-TO-ANALOG CONVERTERS
FEATURES
APPLICATIONS
● TWO D/As IN A 0.3" WIDE PACKAGE
● SINGLE +5V SUPPLY
● HIGH SPEED DIGITAL INTERFACE:
Serial—DAC7800
8 + 4-Bit Parallel—DAC7801
12-Bit Parallel—DAC7802
● MONOTONIC OVER TEMPERATURE
● PROCESS CONTROL OUTPUTS
● ATE PIN ELECTRONICS LEVEL SETTING
● PROGRAMMABLE FILTERS
● PROGRAMMABLE GAIN CIRCUITS
● AUTO-CALIBRATION CIRCUITS
● LOW CROSSTALK: –94dB min
● FULLY SPECIFIED OVER –40OC TO +85OC
DESCRIPTION
12
DAC7802
12-Bit Interface
VREF A
RFB A
CSB
12-Bit MDAC
DAC A
VREF B
AGND A
RFB B
A1
IOUT B
UPD
A0
WR
CLR
CS
12
12-Bit MDAC
DAC B
AGND B
CS
CLR
DAC7800
Serial Interface
UPD B
Serial
12
DAC7801
8-Bit Interface
8 Bits + 4 Bits
8
DAC7801 has a 2-byte (8 + 4) double-buffered
interface. Data is first loaded (level transferred) into
the input registers in two steps for each D/A. Then
both D/As are updated simultaneously. DAC7801 features an asynchronous CLEAR control. DAC7801 is
packaged in a 24-pin 0.3" wide plastic DIP.
CSA
WR
IOUT A
CLK
DAC7800 features a serial interface capable of clocking-in data at a rate of at least 10MHz. Serial data is
clocked (edge triggered) MSB first into a 24-bit shift
register and then latched into each D/A separately or
simultaneously as required by the application. An
asynchronous CLEAR control is provided for poweron reset or system calibration functions. It is packaged
in a 16-pin 0.3" wide plastic DIP.
DAC7802 has a single-buffered 12-bit data word interface. Parallel data is loaded (edge triggered) into the
single D/A register for each D/A. DAC7802 is packaged in a 24-pin 0.3" wide plastic DIP.
UPD A
The DAC7800, DAC7801 and DAC7802 are members of a new family of monolithic dual 12-bit CMOS
multiplying digital-to-analog converters. The digital
interface speed and the AC multiplying performance
are achieved by using an advanced CMOS process
optimized for data conversion circuits. High stability
on-chip resistors provide true 12-bit integral and differential linearity over the wide industrial temperature
range of –40oC to +85oC.
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1990 Burr-Brown Corporation
PDS-1079E
1
DAC7800/01/02
Printed in U.S.A. August, 1993
SPECIFICATIONS
ELECTRICAL
At VDD = +5VDC, VREF A = VREF B = +10V, TA = –40°C to +85°C unless otherwise noted.
DAC7800/7801/7802K
PARAMETER
CONDITIONS
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
MIN
TYP
MAX
12
TA = +25°C
TA = –40°C to +85°C
REFERENCE INPUT
Input Resistance
Input Resistance Match
DIGITAL INPUTS
VIH (Input High Voltage)
VIL (Input Low Voltage)
IIN
(Input Current)
6
MAX
UNITS
±1/2
*
±1
Bits
LSB
LSB
LSB
*
*
*
*
*
*
ppm/°C
nA
nA
*
*
*
2
kΩ
%
*
*
*
*
*
V
V
µA
µA
pF
*
*
*
V
mA
%/%
*
2
0.005
3
5
10
150
10
0.5
14
3
0.8
0.8
±1
±10
10
2
*
*
TA = +25°C
TA = –40°C to +85°C
CIN (Input Capacitance)
POWER SUPPLY
VDD
IDD
Power Supply Rejection
TYP
±1
±1
±3
Measured Using RFB A and RFB B.
All Registers Loaded with All 1s.
Gain Temperature Coefficient(1)
Output Leakage Current
DAC7800/7801/7802L
MIN
4.5
0.2
VDD from 4.5V to 5.5V
5.5
2
0.002
*
*
* Same specification as for DAC7800/7801/7802K.
AC PERFORMANCE
OUTPUT OP AMP IS OPA602.
At VDD = +5VDC, VREF A = VREF B = +10V, TA = +25°C unless otherwise noted. These specifications are fully characterized but not subject to test.
DAC7800/7801/7802K
PARAMETER
CONDITIONS
TYP
MAX
OUTPUT CURRENT SETTLING TIME
To 0.01% of Full Scale
RL = 100Ω, CL = 13pF
0.4
0.8
DIGITAL-TO-ANALOG GLITCH IMPULSE
VREF A = VREF B = 0V
RL = 100Ω, CL = 13pF
0.9
fVREF = 10kHz
–75
–72
*
*
dB
DAC Loaded with All 0s
DAC Loaded with All 1s
30
70
50
100
*
*
*
*
pF
pF
AC FEEDTHROUGH
OUTPUT CAPACITANCE
CHANNEL-TO-CHANNEL ISOLATION
VREF A to IOUT B
VREF B to IOUT A
fVREF A = 10kHz
VREF B = 0V,
Both DACs Loaded with 1s
fVREF B = 10kHz
VREF A = 0V,
Both DACs Loaded with 1s
DIGITAL CROSSTALK
MIN
DAC7800/7801/7802L
MIN
TYP
MAX
UNITS
*
*
µs
*
nV-s
–90
–94
*
*
dB
–90
–101
*
*
dB
*
nV-s
Full Scale Transition
RL = 100Ω, CL = 13pF
0.9
NOTE: (1) Guaranteed but not tested.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC7800/01/02
2
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
At TA = +25°C unless otherwise noted.
PACKAGE
PACKAGE DRAWING
NUMBER(1)
DAC7800KP
DAC7800LP
DAC7800KU
DAC7800LU
16-Pin PDIP
16-Pin PDIP
16-Pin SOIC
16-Pin SOIC
180
180
211
211
DAC7801KP
DAC7801LP
DAC7801KU
DAC7801LU
24-Pin DIP
24-Pin DIP
24-Pin SOIC
24-Pin SOIC
243
243
239
239
DAC7802KP
DAC7802LP
DAC7802KU
DAC7802LU
24-Pin DIP
24-Pin DIP
24-Pin SOIC
24-Pin SOIC
243
243
239
239
MODEL
VDD to AGND ................................................................................. 0V, +7V
VDD to DGND ................................................................................. 0V, +7V
AGND to DGND .......................................................................... –0.3, VDD
Digital Input to DGND ......................................................... –0.3, VDD + 0.3
VREF A, VREF B to AGND ..................................................................... ±25V
VREF A, VREF B to DGND ..................................................................... ±25V
IOUT A , IOUT B to AGND ................................................................. –0.3, VDD
Storage Temperature Range ........................................... –55°C to +125°C
Operating Temperature Range .......................................... –40°C to +85°C
Lead Temperature (soldering, 10s) ................................................ +300°C
Junction Temperature ...................................................................... +175°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure.
positive and negative discharges (100pF in series with 1500Ω)
applied to each digital input.
Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection
methods.
Analog Pins: Each analog pin has been tested to BurrBrown’s analog ESD test consisting of five 1000V positive
and negative discharges (100pF in series with 1500Ω) applied to each pin. AGND, IOUT, and RFB show some sensitivity. Failure to observe ESD handling procedures could result
in catastrophic device failure.
Digital Inputs: All digital inputs of the DAC780X family
incorporate on-chip ESD protection circuitry. This protection
is designed and has been tested to withstand five 2500V
ORDERING INFORMATION
MODEL
DAC7800KP
DAC7800KU(1)
DAC7800LP
DAC7800LU
DAC7801KP
DAC7801KU
DAC7801LP
DAC7801LU
DAC7802KP
DAC7802KU(1)
DAC7802LP
DAC7802LU
RELATIVE ACCURACY
GAIN ERROR
PACKAGE
±1LSB
±3LSB
±1/2LSB
±1LSB
16-Pin DIP
16-Lead SO
16-Pin DIP
16-Lead SO
±1LSB
±3LSB
±1/2LSB
±1LSB
±1LSB
±3LSB
±1/2LSB
±1LSB
1–24
25–99
100+
24-Pin DIP
24-Lead SO
24-Pin DIP
24-Lead SO
24-Pin DIP
24-Lead SO
24-Pin DIP
24-Lead SO
NOTE: (1) Available with Tape and Reel. Add "-TR" to basic model number.
®
3
DAC7800/01/02
DICE INFORMATION
DAC7800 DIE TOPOGRAPHY
DAC7801 DIE TOPOGRAPHY
MECHANICAL INFORMATION
DAC7800
MILS (0.001")
MILLIMETERS
Die Size
Die Thickness
Min. Pad Size
131 x 136 ±5
20 ±3
4x4
3.33 x 3.07 ±0.13
0.51 ±0.08
0.10 x 0.10
Metalization
Aluminum
Substrate Bias: +VDD
DAC7801
MILS (0.001")
MILLIMETERS
Die Size
Die Thickness
Min. Pad Size
131 x 134 ±5
20 ±3
4x4
3.33 x 3.07 ±0.13
0.51 ±0.08
0.10 x 0.10
Metallization
Aluminum
Substrate Bias: +VDD
DAC7802
MILS (0.001")
MILLIMETERS
Die Size
Die Thickness
Min. Pad Size
131 x 121 ±5
20 ±3
4x4
3.33 x 3.07 ±0.13
0.51 ±0.08
0.10 x 0.10
Metalization
DAC7802 DIE TOPOGRAPHY
Substrate Bias: +VDD
®
DAC7800/01/02
4
Aluminum
DAC7800
BLOCK DIAGRAM
PIN CONFIGURATION
VDD
12
10
UPD B
DAC B Register
15
I OUT B
12
16
AGND B
14
RFB B
Bit 11
13
V REF B
Bit 12
4
VREF A
Bit 23
3
R FB A
2
I OUT A
DAC A Register
1
AGND A
12
6
UPD A
12
Control Logic and Shift Register
DAC7800
5
DAC B
Bit 0
DAC A
12
8
7
Data
In
CLK CS
11
9
CLR
DGND
AGND A
1
16
AGND B
I OUT A
2
15
IOUT B
R FB A
3
14
R FB B
13
VREF B
12
VDD
VREF A
4
DAC7800
Top View
DIP
CLK
5
UPD A
6
11
CLR
Data In
7
10
UPD B
CS
8
9
DGND
LOGIC TRUTH TABLE
CLK
UPD A
UPD B
CS
CLR
X
X
X
X
X
0
1
0
X
X
X
1
0
0
X
1
0
0
0
0
0
X
1
1
1
1
X
X
X
X = Don’t care.
FUNCTION
All register contents set to 0’s (asynchronous).
No data transfer.
Input data is clocked into input register (location Bit 23) and previous data shifts.
Input register bits 23 (LSB)—12 (MSB) are loaded into DAC A.
Input register bits 11 (LSB)—0 (MSB) are loaded into DAC B.
Input register bits 23 (LSB)—12 (MSB) are loaded into DAC A, and input register bits 11 (LSB)—0 (MSB)
are loaded into DAC B.
means falling edge triggered.
DATA INPUT FORMAT
DAC7800 Digital Interface Block Diagram
UPD B
UPD A
DAC B Register
DAC A Register
LSB
MSB
Bit
23
Bit
12
LSB
MSB
Bit
11
Bit
0
CLK
Data In
24-Bit
Shift Register
DAC7800 Data Input Sequence
CLK
Data In
Bit 0
MSB
DAC B
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20
LSB
DAC B
MSB
DAC A
Bit 21 Bit 22 Bit 23
LSB
DAC A
®
5
DAC7800/01/02
DAC7800
(CONT)
TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40°C to +85°C.
t5
PARAMETER
CLK
MINIMUM
t1 — Data Setup Time
t2 — Data Hold Time
t3 — Chip Select to CLK,
Update, Data Setup Time
t4 — Chip Select to CLK,
Update, Data Hold Time
t5 — CLK Pulse Width
t6 — Clear Pulse Width
t7 — Update Pulse Width
t8 — CLK Edge to UPD A
or UPD B
0V
t1
15ns
15ns
15ns
DATA
40ns
CS
40ns
40ns
40ns
15ns
UPD A
UPD B
5V
0V
t3
t2
5V
t8
t7
t4
5V
t6
5V
CLR
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t R = t F = 5ns. (2) Timing measurement reference level is VIH + V IL .
2
DAC7801
BLOCK DIAGRAM
PIN CONFIGURATION
VDD
20
DAC7801
DAC A
MS
Input
Reg
AGND A
1
24
AGND B
IOUT A
2
23
I OUT B
RFB A
3
22
RFB B
VREF A
4
21
V REF B
CS
5
20
V DD
19
UPD
DAC A
LS
Input
Reg
4
8
DAC A Register
A1
19
I OUT A
DB0
6
1
AGND A
DB1
7
18
WR
R FB A
DB2
8
17
16
CLR
4
V REF A
DB3
9
16
A0
15
A1
CS
5
21
V REF B
DB4
10
15
A0
WR
18
22
R FB B
DB5
11
14
DB7
CLR
17
23
I OUT B
DGND
12
13
DB6
24
AGND B
DAC A
3
Control Logic
UPD
DAC B
12
DAC B Register
14
4
8
DAC B
MS
Input
Reg
DAC B
LS
Input
Reg
DAC7801
Top View
DIP
2
12
12
6
DB7–DB0
DGND
LOGIC TRUTH TABLE
CLR
UPD
CS
WR
A1
A0
FUNCTION
1
1
0
1
1
1
1
1
1
1
1
X
1
1
1
1
0
0
1
X
X
0
0
0
0
1
0
X
1
X
0
0
0
0
0
0
X
X
X
0
0
1
1
X
X
X
X
X
0
1
0
1
X
X
No Data Transfer
No Data Transfer
All Registers Cleared
DAC A LS Input Register Loaded with DB7–DB0 (LSB)
DAC A MS Input Register Loaded with DB3 (MSB)–DB0
DAC B LS Input Register Loaded with DB7–DB0 (LSB)
DAC B MS Input Register Loaded with DB3 (MSB)–DB0
DAC A, DAC B Registers Updated Simultaneously from Input Registers
DAC A, DAC B Registers are Transparent
X = Don’t care.
®
DAC7800/01/02
6
DAC7801
(CONT)
TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40°C to +85°C.
t1
PARAMETER
MINIMUM
t1 — Address Valid to Write Setup Time
t2 — Address Valid to Write Hold Time
t3 — Data Setup Time
t4 — Data Hold Time
t5 — Chip Select or Update to Write Setup Time
t6 — Chip Select or Update to Write Hold Time
t7 — Write Pulse Width
t8 — Clear Pulse Width
t2
5V
0V
A0–A1
t3
10ns
10ns
30ns
10ns
0ns
0ns
40ns
40ns
t4
5V
0V
DATA
t5
t6
5V
0V
CS, UPD
t7
5V
0V
WR
t8
5V
0V
CLR
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t R = tF = 5ns. (2) Timing measurement reference level is
VIH + V IL
.
2
DAC7802
BLOCK DIAGRAM
PIN CONFIGURATION
VDD
AGND
1
24
I OUT B
12
IOUT A
2
23
R FB B
DAC A Register
R FB A
3
22
V REF B
V REF A
4
21
V DD
CS A
5
20
CS B
(LSB) DB0
6
19
WR
DB1
7
18
DB11 (MSB)
DB2
8
17
DB10
DB3
9
16
DB9
DB4
10
15
DB8
DB5
11
14
DB7
DGND
12
13
DB6
21
DAC7802
CK
12
CS A
CS B
DAC A
5
DAC B
20
12
WR
19
CK
2
IOUT A
3
R FB A
4
V REF A
22
V REF B
23
R FB B
24
I OUT B
1
AGND
DAC B Register
12
12
DGND
18
DAC7802
Top View
DIP
6
TIMING CHARACTERISTICS
DB11–DB0
At VDD = +5V, and TA = –40oC to +85o C.
LOGIC TRUTH TABLE
CSA
CSB
WR
X
X
1
1
1
X
No Data Transfer
0
A Rising Edge on CSA or CSB Loads
Data to the Respective DAC
t1
t2
t3
t4
t5
No Data Transfer
0
1
DAC A Register Loaded from Data Bus
1
0
DAC B Register Loaded from Data Bus
0
0
DAC A and DAC B Registers Loaded
from Data Bus
X = Don’t care.
PARAMETER
FUNCTION
-
MINIMUM
Data Setup Time
Data Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulse Width
20ns
15ns
30ns
0ns
30ns
t1
t2
5V
0V
DATA
t3
t4
CSA, CSB
t5
means rising edge triggered.
5V
5V
WR
NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. t R = t F = 5ns. (2) Timing measurement reference level
VIH + V IL
.
is
2
®
7
DAC7800/01/02
TYPICAL PERFORMANCE CURVES
OUTPUT OP AMP IS OPA602.
TA = +25°C, VDD = +5V.
OUTPUT LEAKAGE CURRENT
vs TEMPERATURE
THD + NOISE vs FREQUENCY
–60
–65
100n
–70
THD + Noise (dB)
Output Leakage Current (A)
1µ
10n
1n
100p
–75
1Vrms
–80
3Vrms
–85
6Vrms
–90
10p
–95
1p
–100
–75
–50
–25
0
+25
+50
+75
+100 +125
10
100
100k
Frequency (Hz)
CHANNEL-TO-CHANNEL ISOLATION
vs FREQUENCY
FEEDTHROUGH vs FREQUENCY
–20
0
–30
–10
–40
–20
–50
–30
Feedthrough (dB)
Crosstalk (dB)
10k
1k
Temperature (°C)
–60
–70
–80
–90
–40
–50
–60
–70
–80
–100
–110
–90
–120
–100
1k
10k
1M
100k
10M
1k
10k
1M
100k
Frequency (Hz)
10M
Frequency (Hz)
PSRR vs FREQUENCY
FREQUENCY RESPONSE
+30
70
CF = 0pF
+20
CF = 5pF
60
+10
50
0
40
PSRR (dB)
Gain (dB)
DAC Loaded w/0s
–10
CF = 10pF
–20
30
20
–30
10
–40
0
DAC Loaded w/1s
–10
–50
1k
10k
100k
1M
10M
1k
100k
Frequency (Hz)
Frequency (Hz)
®
DAC7800/01/02
10k
8
1M
DISCUSSION OF
SPECIFICATIONS
of the ladder regardless of the input code. The input resistance
at VREF is therefore constant and can be driven by either a
voltage or current, AC or DC, positive or negative polarity,
and have a voltage range up to ±20V.
RELATIVE ACCURACY
This term, also known as end point linearity or integral
linearity, describes the transfer function of analog output to
digital input code. Relative accuracy describes the deviation
from a straight line, after zero and full scale errors have been
adjusted to zero.
VREF A
R
2R
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output when the input code changes by 1LSB.
A differential nonlinearity specification of 1LSB maximum
guarantees monotonicity.
R
R
2R
2R
2R
2R
R RFB A
IOUT A
AGND
DB11
(MSB)
GAIN ERROR
Gain error is the difference between the full-scale DAC
output and the ideal value. The ideal full scale output value
for the DAC780X is –(4095/4096)VREF . Gain error may be
adjusted to zero using external trims as shown in Figures 5
and 7.
DB10
DB9
DB0
(LSB)
FIGURE 1. Simplified Circuit Diagram for DAC A.
A CMOS switch transistor, included in series with the ladder
terminating resistor and in series with the feedback resistor,
RFB A, compensates for the temperature drift of the ON
resistance of the ladder switches.
OUTPUT LEAKAGE CURRENT
The current which appears at IOUT A and IOUT B with the DAC
loaded with all zeros.
Figure 2 shows an equivalent circuit for DAC A. COUT is the
output capacitance due to the N-channel switches and varies
from about 30pF to 70pF with digital input code. The current
source ILKG is the combination of surface and junction leakages to the substrate. ILKG approximately doubles every 10°C.
RO is the equivalent output resistance of the D/A and it varies
with input code.
OUTPUT CAPACITANCE
The parasitic capacitance measured from IOUT A or IOUT B to
AGND.
CHANNEL-TO-CHANNEL ISOLATION
The AC output error due to capacitive coupling from DAC A
to DAC B or DAC B to DAC A.
R
RFB A
VREF A
MULTIPLYING FEEDTHROUGH ERROR
The AC output error due to capacitive coupling from VREF to
IOUT with the DAC loaded with all zeros.
R
DIN VREF
x
4096
R
RO
ILKG
IOUT A
COUT
AGND A
OUTPUT CURRENT SETTLING TIME
The time required for the output current to settle to within
+0.01% of final value for a full scale step.
FIGURE 2. Equivalent Circuit for DAC A.
INSTALLATION
DIGITAL-TO-ANALOG GLITCH ENERGY
The integrated area of the glitch pulse measured in nanovoltseconds. The key contributor to digital-to-analog glitch is
charge injected by digital logic switching transients.
ESD PROTECTION
All digital inputs of the DAC780X incorporate on-chip ESD
protection circuitry. This protection is designed to withstand
2.5kV (using the Human Body Model, 100pF and 1500Ω).
However, industry standard ESD protection methods should
be used when handling or storing these components. When
not in use, devices should be stored in conductive foam or
rails. The foam or rails should be discharged to the destination socket potential before devices are removed.
DIGITAL CROSSTALK
Glitch impulse measured at the output of one DAC but
caused by a full scale transition on the other DAC. The
integrated area of the glitch pulse is measured in nanovoltseconds.
POWER SUPPLY CONNECTIONS
The DAC780X are designed to operate on VDD = +5V +10%.
For optimum performance and noise rejection, power supply
decoupling capacitors CD should be added as shown in the
application circuits. These capacitors (1µF tantalum recommended) should be located close to the D/A. AGND and
CIRCUIT DESCRIPTION
Figure 1 shows a simplified schematic of one half of a
DAC780X. The current from the VREF A pin is switched
between IOUT A and AGND by 12 single-pole double-throw
CMOS switches. This maintains a constant current in each leg
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DGND should be connected together at one point only,
preferably at the power supply ground point. Separate returns
minimize current flow in low-level signal paths if properly
connected. Output op amp analog common (+ input) should
be connected as near to the AGND pins of the DAC780X as
possible.
DATA INPUT
ANALOG OUTPUT
MSB ↓
↓ LSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
–VREF (4095/4096)
–VREF (2048/4096) = –1/2VREF
–VREF (1/4096)
0 Volts
TABLE II. Unipolar Output Code.
WIRING PRECAUTIONS
VDD VREF A
+5V
To minimize AC feedthrough when designing a PC board,
care should be taken to minimize capacitive coupling between the VREF lines and the IOUT lines. Similarly, capacitive
coupling between DACs may compromise the channel-tochannel isolation. Coupling from any of the digital control or
data lines might degrade the glitch and digital crosstalk
performance. Solder the DAC780X directly into the PC
board without a socket. Sockets add parasitic capacitance
(which can degrade AC performance).
CD
1µF
RFB A
IOUT A
DAC A
DAC780X
AMPLIFIER OFFSET VOLTAGE
The output amplifier used with the DAC780X should have
low input offset voltage to preserve the transfer function
linearity. The voltage output of the amplifier has an error
component which is the offset voltage of the op amp multiplied by the “noise gain” of the circuit. This “noise gain” is
equal to (RF / RO + 1) where RO is the output impedance of the
D/A IOUT terminal and RF is the feedback network impedance. The nonlinearity occurs due to the output impedance
varying with code. If the 0 code case is excluded (where RO
= infinity), the RO will vary from R to 3R providing a “noise
gain” variation between 4/3 and 2. In addition, the variation
of RO is nonlinear with code, and the largest steps in RO occur
at major code transitions where the worst differential
nonlinearity is also likely to be experienced. The nonlinearity
seen at the amplifier output is 2VOS – 4VOS /3 = 2VOS/3.
Thus, to maintain good nonlinearity the op amp offset should
be much less than 1/2LSB.
–
A1
+
VOUT A
–
A2
+
VOUT B
RFB B
DAC B
DGND
C1
10pF
AGND A
IOUT B
VREF B
AGND B
C2
10pF
A1, A2 OPA602 or 1/2 OPA2107.
DAC7802 has a single analog
common, AGND.
FIGURE 3. Unipolar Configuration.
VDD
+5V
CD
1µF
+
VIN A
R1
100Ω
V REF A
RFB A R2
IOUT A
DAC A
UNIPOLAR CONFIGURATION
Figure 3 shows DAC780X in a typical unipolar (two-quadrant) multiplying configuration. The analog output values
versus digital input code are listed in Table II. The operational amplifiers used in this circuit can be single amplifiers
such as the OPA602, or a dual amplifier such as the OPA2107.
C1 and C2 provide phase compensation to minimize settling
time and overshoot when using a high speed operational
amplifier.
If an application requires the D/A to have zero gain error, the
circuit shown in Figure 4 may be used. Resistors R2 and R4
induce a positive gain error greater than worst-case initial
negative gain error. Trim resistors R1 and R3 provide a
variable negative gain error and have sufficient trim range to
correct for the worst-case initial positive gain error plus the
error produced by R2 and R4.
AGND A
IOUT B
DAC B
V REF B
DGND
47Ω
C1 10pF
–
A1
+
VOUT A
RFB B R4
DAC780X
R3
100Ω
47Ω
AGND B
C2 10pF
–
A2
+
VOUT B
A1, A2 OPA602 or 1/2 OPA2107.
DAC7802 has a single analog
common, AGND.
V IN B
FIGURE 4. Unipolar Configuration with Gain Trim.
The operational amplifiers used in this circuit can be single
amplifiers such as the OPA602, a dual amplifier such as the
OPA2107, or a quad amplifier like the OPA404. C1 and C2
provide phase compensation to minimize settling time and
overshoot when using a high speed operational amplifier.
The bipolar offset resistors R5–R7 and R8–R10 should be
ratio-matched to 0.01% to ensure the specified gain error
performance.
BIPOLAR CONFIGURATION
Figure 5 shows the DAC780X in a typical bipolar (fourquadrant) multiplying configuration. The analog output values versus digital input code are listed in Table III.
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10
If an application requires the D/A to have zero gain error, the
circuit shown in Figure 6 may be used. Resistors R2 and R4
induce a positive gain error greater than worst-case initial
negative gain error. Trim resistors R1 and R3 provide a
variable negative gain error and have sufficient trim range to
correct for the worst-case initial positive gain error plus the
error produced by R2 and R4.
DATA INPUT
ANALOG OUTPUT
MSB ↓
↓ LSB
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0000
+VREF (2047/2048)
+VREF (1/2048)
0 Volts
–VREF (1/2048)
–VREF (2048/2048)
TABLE III. Bipolar Output Code.
R1
20k Ω
+5V
VDD VREF A
R2
20k Ω
–
CD +
1µF
A2
R3
10k Ω
VOUT A
+
RFB A
C1
10pF
IOUT A
DAC A
–
A1
AGND A
+
DAC7802 has a single analog common, AGND.
A1–A4, OPA602 or 1/2 OPA2107.
DAC780X
RFB B
C2
10pF
IOUT B
DAC B
AGND B
–
A3
+
R5
10k Ω
R6
20k Ω
R4
20k Ω
–
DGND
A4
VOUT B
+
VREF B
FIGURE 5. Bipolar Configuration.
APPLICATIONS
12-BIT PLUS SIGN DACS
For a bipolar DAC with 13 bits of resolution, two solutions
are possible. As shown in Figure 7, the addition of a precision
difference amplifier and a high speed JFET switch provides
a 12-bit plus sign voltage-output DAC. When the switch
selects the op amp output, the difference amplifier serves as
a non-inverting output buffer. If the analog ground side of the
switch is selected, the output of the difference amplifier is
inverted.
DAC1 and DAC2 can be updated in parallel with a single word
to set the center frequency of the filter. DAC 4, which makes
use of the uncommitted op amp in UAF42, sets the Q of the
filter. DAC3 sets the gain of the filter transfer function without
changing the Q of the filter. The reverse is also true.
The center frequency is determined by fC = 1/2πRC where R
is the ladder resistance of the D/A (typical value, 10kΩ) and
C the internal capacitor value (1000pF) of the UAF42. External capacitors can be added to lower the center frequency of
the filter. But the highest center frequency for this circuit will
be about 16kHz because the effective series resistance of the
D/A cannot be less than 10kΩ.
Another option, shown in Figure 8, also produces a 12-bit
plus sign output without the additional switch and digital
control line.
DIGITALLY PROGRAMMABLE ACTIVE FILTER
DAC780X are shown in Figure 9 in a digitally programmable
active filter application. The design is based on the statevariable filter, Burr-Brown UAF42, an active filter topology
that offers stable and repeatable filter characteristics.
Note that the ladder resistance of the D/A may vary from
device to device. Thus, for best tracking, DAC2 and DAC3
should be in the same package. Some calibration may be
necessary from one filter to another.
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R5
20k Ω
+5V
VDD VIN A
R6
20k Ω
–
CD +
1µF
+
VREF A
RFB A
R7
10k Ω
R2
47 Ω
C1
10pF
IOUT A
DAC A
RFB B
+
DAC7802 has a single analog common, AGND.
A1–A4, OPA602 or 1/2 OPA2107.
R4
47 Ω
C2
10pF
IOUT B
DAC B
–
A1
AGND A
DAC7802
AGND B
–
A3
+
R9
Ω
10kΩ
10k
R8
20k Ω
VREF B
R3
100 Ω
DGND
VOUT A
A2
R1
100 Ω
R10
20k Ω
–
VOUT B
A4
+
VIN B
FIGURE 6. Bipolar Configuration with Gain Trim.
+15V
2
+10V
6
REF102
+5V
4
VDD
CD
1µF
VREF A
RFB A
IOUT A
DAC A
AGND A
C1
10pF
R
A1
R
2
DAC780X
6
R
3
R
Sign Control
DAC B
DGND
VREF B
DG188
AGND B
DAC7802 has a single analog common, AGND.
A1 OPA602 or 1/2 OPA2107.
FIGURE 7. 12-Bit Plus Sign DAC.
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12
INA105
±10V
13 Bits
+15V
2
+10V
6
REF102
+5V
4
VDD
CD
1µF
VREF A
RFB A
C1
10pF
IOUT A
DAC A
R
A1
AGND A
R
2
DAC780X
R
INA105
A2
AGND B
VREF B
DGND
±10V
13 Bits
3
C2
10pF
IOUT B
DAC B
6
R
RFB B
1
DAC7802 has a single analog common, AGND.
A1 OPA602 or 1/2 OPA2107.
FIGURE 8. 13-Bit Bipolar DAC.
Q Adjust
VREF 2
DAC 2
f C Adjust
V REF 4
IOUT 2
DAC 4
AGND 2
VREF 1
I OUT 4
AGND 4
1/2 DAC780X
IOUT 1
DAC 1
R FB 4
AGND 1
DAC780X
High-Pass Out
Filter Input
13
R
Low-Pass
Out
Band-Pass
Out
8
7
1
14
5
VREF 3
I OUT 3
DAC 3
C
R
C
12
AGND 3
1/2 DAC780X
Gain Adjust
6
3
R
R
UAF 42
R = 50k Ω ±0.5%
C = 1000pF ±0.5%
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2
4
FIGURE 9. Digitally Programmable Universal Active Filter.
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