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Characterization of DTMOST Structures to be used in Bandgap Reference Circuits in
0.13µm CMOS Technology.
21 November 2003.
V. Gromov (vgromov@nikhef.nl).
ET NIKHEF, Amsterdam.
Abstract.
This document describes objectives and method
used to characterize DTMOST structures in the
0.13µm CMOS technology. The temperature
dependence of the Id(Vgs) relationship is measured
and parameterized into a simple mathematical
model. On the basis of this model performances of
two basic Bandgap reference (BGR) circuits have
been evaluated.
The classical voltage summing BGR circuit
demonstrates
Vref=464mV±1.25mV
in
the
temperature range from 0ºC up to 80ºC when ideal
opamp and current sources are used. Theoretically
this circuit is capable to operate at power supply
voltages (Vdd) as low as Vref+Vdssat≈ 600mV.
The classical current summing BGR circuit
delivers a current as well as a voltage, both
remaining stable within a ±0.3% margin in the
temperature range from 0ºC up to 80ºC when ideal
opamp and current sources are used. Because of the
current summing architecture theoretically this
current summing BGR circuit can operate with a
Vdd down to 350mV.
Introduction.
An on-chip reference circuit insensitive to
temperature and power supply variations is a crucial
component for high quality A/D and D/A converters.
With lower power supply voltages in present deep
submicron CMOS technologies (0.13µm) a design of a
reference on-chip becomes an important objective.
The classical voltage summing BGR (see Fig.1)
featuring a parasitic p-n-p [1] (p-diffusion in N-well)
does not fit into a 0.13µm CMOS technology with a
maximum Vdd of 1.2V.
A current summing architecture (see Fig.2) can
operate at Vdd down to 0.84V [2]. On top of it, this
solution provides both a stable voltage and/or a stable
current at the output. This circuit could be successfully
implemented in 0.13µm CMOS technology. There is a
fundamental limitation here due to the voltage drop
across a silicon p-n junction. The minimum Vdd is
therefore given by:
Vddmin = Vbep-n junction + Vds sat ≈ 800mV.
I
I
Iref
R3
R4
R1
D
Fig.2.
reference.
nD
Classical
current
summing
Bandgap
Recently Anne-Johan Annema among others
proposed to use a new structure called a dynamic
threshold MOS transistor (DTMOST) [3]. A DTMOST
is in fact a p-channel MOS (PMOST) transistor with
gate, drain and substrate contacts connected together
(see Fig.3).
Source
Gate
metal +
oxide
Drain
Substrate
Vref
P-diffusion
R2
I
N-well
contact
Floating N-well (substrate)
I
R1
D
P-diffusion
Fig.3. Cross section of a DTMOST structure.
nD
Fig.1. Classical voltage summing Bandgap reference.
According to Annema, this device can be seen as a
PMOST with a dynamically regulated threshold: every
change in Vgs causes a change in threshold voltage. The
drain current is primarily determined by the voltage
across the source-substrate junction. This results in an
2
ideal exponential relationship between Vgs and Id. We
can consider this two-terminal device as a diode, but
with much lower threshold voltage (Vthr=200mV) than
a conventional diode (Vthr =650mV). This fundamental
feature can be combined with a bandgap compensation
technique to design a stable reference circuit. Another
feature of this device is that the matching of the
DTMOST’s is about twice as good as the matching
between PMOSTs of the same size operating at the same
current. Moreover batch-to-batch variations of
DTMOST’s are about half the value of their PMOST
counterparts [3]. He has successfully implemented
various BGR circuits featuring DTMOST’s in 0.35µm
CMOS technology in 1999 [3].
Nowadays we step into 0.13µm CMOS and face the
challenge to keep our design within the 1.2V power
supply rails. The DTMOST structure seems to be
interesting to look at thanks to its remarkable diode-like
behaviour in combination with its low voltage threshold
feature. These features let us consider the DTMOST as a
key component in future very low supply voltage BGR
designs.
In order to design and verify a complete BGR circuit
the DTMOST structure needs to be parameterized and
modeled.
The test structures.
Although many various structures were available on
the chip we limited ourselves to the enclosed-gate ones.
One reason is their better radiation hardness, which
needs in our applications, the other reason is that the
symmetrical layout will result in better matching
properties and might exclude some unwanted and
unexpected effects.
The measured structures are (see Fig.4, Fig.5):
a)
4-terminal enclosed-gate PMOS with gate
width of 10µm and gate length of 0.12µm,
b)
4-terminal enclosed-gate PMOS with gate
width of 10µm and gate length of 0.6µm
c)
4-terminal enclosed-gate PMOS with gate
width of 10µm and gate length of 2µm.
Drain
Gate
metal + oxide
P-diffusion
Gate
metal + oxide
Source
P-diffusion
Substrate
P-diffusion
N-well
contact
Floating N-well (substrate)
Fig.5. Cross section of the Test Structure.
Test set-up.
The DTMOST structure characterization consists in
the determination of the Id(Vgs) relationship at various
temperatures. A chip with various test structures from an
experimental 0.13µm CMOS submission was measured
in a temperature chamber. A Picoammeter/voltage
source device carried out the measurements under
control of LabVIEW software. A high precision
thermometer with a remote probe is used for accurate
monitoring of the temperature (see Fig.6).
Labview
software
GPIB bus
Heraeus
Heraeus
Temperature chamber
Temperature
control
0ºC≤Temp≤80ºC
Current
measurements /
voltage control
Chip with the test
structures on it.
Thermometer
Keithley 487
Picoammeter/
voltage source
Fig.6. Diagram of the Test Set-up.
The photograph below shows the lay-out of the test
set-up. (see Fig.7).
Heraeus
Temperature chamber
Keithley 487
Picoammeter/
voltage source
P-diffusion
(source)
Drain
Heraeus
Thermometer
Metal (gate)
P-diffusion (drain)
Floating N-well (substrate)
Fig.4. Top view of the Test Structure.
Fig.7. Measurement Set-up.
3
DTMOST device compared with a conventional
diode.
In order to illustrate all the features already
mentioned it is interesting to compare the Id(Vgs)
relationship of a conventional diode with that of a
DTMOST structure in 0.13µm CMOS technology (see
Fig.8, Fig.9).
650mV while the DTMOST configuration is exponential
within a region from 100mV to 220mV (see Fig.11).
2.5 10
5
I, A
2 10
Conventional
diode
configuration
DTMOST
configuration
5
Common Source
Common Gate
Measured points
1.5 10
m4
j2
N well
U
Drain P_E_10_0.12
or
Drain P_E_10_0.6
or
Drain P_E_10_2
5
m3
j2
1 10
I
5 10
10
5
6
7
0
Fig.8. DTMOST configuration on the basis of a
PMOS structure.
Common Source
Common Gate
Uthr DIODE =
650mV
Uthr DTMOST =
200mV
0.1
0.2
0.3
0.4
0.5
0.6
0.7
 m3
j1
j1
Um4
, Volts
0.1
0.8
0.8
Fig.10. Current-to-voltage characteristics for both
DTMOST configuration and conventional diode
configuration. Gate area is 10µm/0.6µm.
N well
U
I
2.5 10
1 10
5
4
Exponential fit function
I(U)=37 10-10 [EXP(30 U)-1]
I, A
Conventional
diode configuration
DTMOST
configuration
5
Region
of
exponential
m4
j2
(“ideal diode”)
m3
j  2 behaviour
….220mV
f(100mV
x)
1 10
Fig.9. Conventional diode configuration (p-diffusion
in N-well) on the basis of a PMOS structure.
The measured current-to-voltage characteristics are
given in Figure 10 and 11. The operational threshold of a
DTMOST is about 200mV whereas that of a
conventional diode is in the vicinity of 650mV (see
Fig.10). This feature is crucial in modern low-voltage
CMOS circuit designs.
The exponential behaviour of the Id(Vgs)
relationship is of primary importance because it enables
us to construct a current source which delivers a current
that is proportional to the absolute temperature (PTAT).
This can be used to implement a mechanism to
compensate temperature drift [4]. The conventional
diode has an exponential Id(Vgs) relationship above
1 10
6
7
10 1 10 7
0
0.01
0.1
0.2
0.3
0.4
0.5
0.6
0.7
m4  m3  x
1
j1
, jVolts
U
Fig.11. Logarithmic scale. Current-to-voltage
characteristics for both DTMOST configuration and
conventional diode configuration. Gate area is
10µm/0.6µm.
0.8
0.8
4
DTMOST structures on the chip.
The measured points of the Id(Vgs) relationship are
given in Figure12 for all the test DTMOST structures.
I, A
0.5 10
5
preferable candidate (region of exponential behaviour is
from 0.1µA up to 2µA).
Drain P_E_10_0.6
4 10
6

m20 3 10
j2
6
Drain P_E_10_0.12
1 10
Drain P_E_10_0.12

51 10
5
Exponential fit function
I(U)=6.9 10-10 [EXP(33 U)-1]
I, A
1 10
6
Exponential
behaviour range
0.07µA…3µA
m20
j2
n20
j2
ff( x )
k20
j2
6
2 10
1 10
7
Drain P_E_10_2
1 10
6
8
10 1 10 8
0.1
0.12
0.14
0.16
1.438 10
8
0
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0.26
0.28
U, Volts
0.1
k80
j1
0.3
0.3
0.2
0.22
1 10
Exponential fit function
I(U)=30 10-10 [EXP(30 U)-1]
I, A
0.26
0.28
0.3
0.3
Drain P_E_10_2
5
Exponential fit function
I(U)=24 10-10 [EXP(30 U)-1]
I, A
1 10
6
n20
j2
Exponential
behaviour range
0.09µA…0.45µA
ff( x )
5
1 10
0.24
Fig.14. Current-to-voltage characteristic of the
DTMOST in logarithmic scale. (gate area is:
10µm/0.12µm)
Fig.12. Current-to-voltage characteristics of the
DTMOSTs at room temperature (gate areas are: 10µm
/0.6µm, 10µm /0.12µm, 10µm /2µm).
The width of the region of the exponential behaviour
is the criteria to determine the best candidate for a
bandgap reference circuit.
0.18
x
U,k80Volts
j1
0.1
1 10
7
1 10
8
Drain P_E_10_0.6
6
1 10
Exponential
behaviour range
0.1µA…2µA
k20
j2
ff( x )
1 10
7
1 10
8
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0.26
0.28
x
U, k80
Volts
j1
Fig.15. Current-to-voltage characteristic of the
DTMOST in logarithmic scale. (gate area is:
10µm/2µm)
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0.26
0.28
0.3
x
j1
U, k80
Volts
Fig.13. Current-to-voltage characteristic of the
DTMOST in logarithmic scale. (gate area is:
10µ/0.6µm)
The minimum channel length DTMOST structure
(gate dimensions are 10µm/0.12µm) shows the widest
region of exponential behaviour in the range from
0.07µA up to 3µ (see Fig.13-Fig.15). On the other hand
it seems to be risky to use it for a high quality analogue
design from the point of view of spread and mismatch.
The DTMOST with a gate 10µm/0.6µm is the most
Current-to-voltage characteristics at various
temperatures.
To be able to construct an appropriate model, the
DTMOST current-to-voltage characteristic must be
measured at various temperatures. The theory predicts
that the voltage drop on a DTMOST is Conversely
Proportional To the Absolute Temperature (CTAT) at a
constant bias current see Figure.16-Figure.18. The
steepness of the U(T) relation depends on the bias
current and on the geometry of the DTMOST device and
varies between 4mV/10ºC and 10mV/10 ºC (see Fig.16Fig.18).
0.3
5
5 10
Temp=80ºC
0.5 10
6
I, A
Temp=70ºC
Temp=70ºC
n0
j2 
6
4 10
n10
j2
k80
j2

k70 4 10
j2
Temp=80ºC
I, A
5
6
n20
j2
k60
j2
n30 3 10
j2
6
k50
j  23 10
6
n40
j2
Temp=0ºC
k40
j2
Temp=0ºC
n50
j2
6
2 10
n60
j2
k30
j2 
6
2 10
k20
j2
n70
j2
n80 1 10 6
j2
k10
j2
6

k0 1 10
j2
10
8
0.1
10
7
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
U, k80
Volts
j1
0.1
0.15
0.26
0.18
0.21
0.24
0.26
j1
U, Volts
n0
0.26
Fig.16. Current-to-voltage characteristic of the
DTMOST at various temperatures in the range 0ºC
…80ºC with 10ºC interval (gate areas is 10µm /0.6µm).
5 10
0.13
0.1
0.29
0.29
Fig.18. Current-to-voltage characteristic of the
DTMOST at various temperatures in the range 0ºC
…80ºC with 10ºC interval (gate areas is 10µm /0.12µm).
The extrapolation of the U(T) dependence down to
absolute zero temperature gives an estimation of the
bandgap voltage in the DTMOST device (see Fig.19).
The estimated bandgap voltage is approximately 410mV
for the DTMOST with gate dimensions 10µm/0.6µm.
6
I, A
Temp=80ºC
m80
j2
6
4 10
m70
j2
Temp=70ºC
Estimated Bandgap voltage
≈ 410 mV
400
U, mV
m60
j2
BG
i1
m50 3 10 6
j2
BG
i  2 300
m40
j2
BG
i3
m30
j2
6
2 10
m20
j2
Temp=0ºC
I=2µA
F1( z )
Linear fits
F2( z )
m10
j2
F3( z )
200
I=1µA
m0
6
j  2 1 10
I=0.5µA
10
7
100
0.1
0.1
0.13
0.15
0.18
0.21
0.24
0.26
U, Volts
m80
j1
Fig.17. Current-to-voltage characteristic of the DTMOST
at various temperatures in the range 0ºC …80ºC with
10ºC interval (gate areas is 10µm /2µm).
0.29
0.29
250
200
150
100
50
0
50
BG ºC
BG  BG  z  z  z
Temp,
i0
i0
i0
Fig.19. Voltage across the DTMOST at various currents
as a function of temperature (gate areas is
10µm/0.6µm).
100
6
Evaluation of the Performance of the Voltage
Summing Bandgap Reference circuit.
Having
characterized
current-to-voltage
dependences at various temperatures we are able to
evaluate the performance of some basic BGR circuits.
The most common of them is a voltage summing BGR
circuit (see Fig.20). Every component of the circuit
except for the DTMOST’s themselves, have been
considered ideal when estimating the temperature
stability of the output voltage (Vref). In a real design a
full temperature dependent SPICE simulation will, of
course be needed, including non-ideal components.
Ideal
Current source
Fig.21). The quiescent operation point occurs at
V(A)=V(B) (see Fig.21)
Volts
0.25
V(B)
0.24
0.22
Measured data points
V(A)
0.2
U30( y )
Linear interpolation
function
Stable operating
point occurs at
0.18
U30
y
y 27000
4
I=1.77µA, U=205mV
0.16
Ideal
Current source
0.14
Vref
0.12
R2
0.1 0.1
7
5 10
6
0.5 10
Ideal
OPAMP
1.5 10
6
2 10
6
I ,A
2.5 10
6
6
3 10
6
3 10
6
y
Fig.21. Voltage at the inputs of the OPAMP as a
function of current at 30ºC .
V(A)
I
1 10
I
V(B)
R1
V(C)
#1
#4
The temperature drift of the voltages in the stable
operation point is conversely proportional to the absolute
temperature (CTAT) (see Fig.22). The voltage drop
across the resistor R1 is on the contrary directly
proportional to the absolute temperature (PTAT) (see
Fig22).
I/4
250
DTMOSTs 10µm/0.6µm
mV
200
Fig.20. Schematic of a semi-ideal voltage summing
BGR circuit with the DTMOST’s (gate dimensions
10µm /0.6µm).
V(A)=V(B)
CTAT
150
UU1
i1  0
UU12
i1  0
V(B)-V(C)
PTAT
100
The quiescent current in the stable operation point of
the circuit is given as
Io(T) = [kT/e] ln(A) [1/R1], where
T is the absolute temperature,
k is Boltzmann’s constant,
e is the electron charge,
A is the ratio of DTMOST’s areas in both branches
of the circuit.
To keep the operating point of the DTMOST’s
within the region of exponential behaviour
(0.1µA<Io<2µA) the parameter A is chosen equal to 4
and R1 is 30kΩ.
A simple linear interpolation was used to form a
continuous function out of the measured data values (see
50
0
0
10
20
30
40
50
60
70
i1 10  i1 10
Temp, ºC
Fig.20.
Fig. 22. Temperature drift of the voltages in the voltage
summing BGR circuit.
Figure 22 shows the different slopes of the curves.
For the precise compensation of the temperature drifts
the following condition must be met:
R2 = R1 [Slope(CTAT)/Slope (PTAT)]
80
7
Under this condition the output voltage (see Fig.23)
Vref=464mV remains temperature insensitive within a
margin of ±1.25mV (see Fig 21).
Each of the ideal current sources drives current
(see Fig.25) equal to
I
I=i1(PTAT) + i2(PTAT)
466
1.828
µA
Vref, mV
UU2
i1 1.6
30 II2 5.4 464
i1
Temperature drift
of the reference voltage
is ±1.25mV
160
II2
i1
(±0.3%)within
0ºC…80ºC range
463
462
i1
1.8
465
UU2
i1
2
10
0
50
40
30
20
1.4
i2
1.2
60
70
 i1 10
i1 10ºC
Temp,
80
1.052
1
0
10
20
Fig. 23. Temperature drift of the reference voltage (Vref)
(R1=30kΩ, R2=162 kΩ,).
Evaluation of the Performance of the Current
Summing Bandgap Reference circuit.
The current summing BGR circuit employs the
same mechanism of temperature compensation as the
voltage summing BGR (see Fig.24). This circuit delivers
a stable reference current that can be converted into a
stable voltage if necessary.
30
40
50
60
70
80
10  i1 10
Temp,i1 ºC
0
80
Fig.25. Temperature drift of the currents in the
current summing BGR circuit (R3=R4=160kΩ,
R1=30kΩ).
The sum of the partial currents (i1, i2) is I=2.882µA
and remains constant within ±0.3% in a temperature
range from 0ºC to 80ºC (see Fig.26).
2.889
I, uA
2.89
2.886
Ideal
Current source
Ideal
Current source
Ideal
Current source
2.882
UU2
i1
160
Iref
Ideal
OPAMP
I
I
II2
i1
2.878
± 8nA (± 0.3%)
within 0ºC…80ºC
range
2.874
i2
2.872 2.87
i1
0
R4
R3
R1
#1
0
10
20
30
40

50
60
70

Temp, ºCi1 10  i1 10
Fig. 26. Temperature drift of the reference current
(Iref) (R3=R4=160kΩ, R1=30kΩ).
#4
DTMOSTs 10µm/0.6µm
Fig.24. Schematic of a semi-ideal current summing
BGR circuit with the DTMOST’s (gate dimensions
10µm /0.6µm).
80
80
8
Conclusions.
The current-to-voltage relationship Id(Vgs) of the
DTMOST’s have been measured at various
temperatures. The DTMOST structures came from an
experimental submission in 0.13µm CMOS technology.
The measurements have been the basis to evaluate
performances of two principal bandgap reference (BGR)
circuits assuming ideal opamps and ideal current sources
inside.
The measured DTMOST structures show a valid
exponential behaviour, which can be used to construct a
device with a PTAT characteristic.
Within a temperature range from 0ºC to 80ºC the
voltage summing BGR circuit can provide a reference
voltage of Vref=464mV±1.25mV and supposedly is
capable to operate at a Vdd as low as 600mV. In the
same temperature range, the current summing BGR
circuit
can
generate
a
reference
current
Iref=2.882µA±8nA (or ±0.3%) and would supposedly be
able to operate at a supply voltage down to 350mV.
The DTMOST structure seems to be an attractive
candidate for very low-voltage bandgap reference
circuits.
Acknowledgements.
I thank dr. ir. A.J. Annema of MESA Institute,
University of Twente, Enschede, for giving me initial
information on the DTMOST featuring bandgap
reference circuits and for an advice to characterize the
DTMOST’s. I thank Paulo Moreira and Federico Faccio
of CERN, Geneva for sending me two test chips from
their experimental 0.13µm CMOS submission.
I thank Ruud Kluit for giving me productive ideas
on the test facilities and Fred Schimmel for his help in
handling LabVIEW software.
References.
[1] Jiang Yueming and Lee Edward, Design of LowVoltage Bandgap Reference Using Transimpedance
Amplifier, IEEE TCAS II, vol.47, pp.552-555.34, pp. 7680, June 2000.
[2] Hironori Banba, Hitoshi Shiga et al , A CMOS
Bandgap Reference Circuit with Sub-1-V Operation,
IEEE Journal of Solid-State Circuits, vol.34, No.5, May
1999.
[3] Anne-Johan Annema , Low-Power Bandgap
References Featuring DTMOST’s, IEEE Journal of
Solid-State Circuits, vol.34, No.7, July 1999.
[4] Robert Pease, The Design of Band-Gap
Reference Circuits: Trials and Tribulations. IEEE 1990
Bipolar Circuits and Technology Meeting, pp 214-218,
1990.