Download Current mirror design.pps

Current mirror design
In AMIS CMOS 07
by Roman Prokop
Simple current mirror
VGS  VT 0  VGS
Saturace
VDS  VGS ,
recommende d VGSMIN  200mV
ID 
K p .W
2.L
(VGS  VT 0 ) 2
W / L calculatio n
W
I D .2

L K p (VGS ) 2
AMIS CMOS 07 param
VT0 & KP = f (T, process) graphs
• NMOS
Process
VT0 [V]
Kp [A/V2]
Temp [°C]
Typ
0.75
9. 10-5
27
Fast
0.7
1.75 .10-4
-50
Fast
0.45
7 .10-5
150
Slow
1.00
1.25 .10-4
-50
Slow
0.75
5 .10-5
150
W/L calculation for typ parameters
ID 
K p .W
2.L
(VGS  VT 0 ) 2
Choose ∆VGS= 250 mV
&
ID= 20 μA
W
I D .2

 7.11  7
2
L K p _ typ (VGS )
Ideal Vds1=Vds2
solution
- Decrease the Vds influence  large L
- cascoda
ID 
K p .W
2.L
(VGS  VT 0 ) 2 .(1  .VDS )  simplified
min. ∆VGS
∆VGS
I D .2.L
VGSMIN 
 179mV
Kpmax .W
VGS  VT 0  VGS
max.
VGSMAX 
I D .2.L
 335mV
Kpmin .W
 the worst cases
VGS _ fast50  0.7  0.179  0.879 V
VGS _ slow150  0.75  0.335  1.085 V
VGS _ fast150  0.45  0.28  0.733 V
VGS _ slow50  1.00  0.212  1.212 V
Then input current can vary between (even for fix (dummy) resistor R)
Vcc  VGSM 1
5  (0.75  0.25)
;
I INtyp 
 20 A
R
200k
5  0.733
5  1.212
I IN max 
 21.335 A
I IN max 
 18.94 A
200k
200k
I IN 
150°C hipo(min)IIN ↑
-50°C hipo(max)IIN ↓
How to get fixed voltage for current mirror biasing ?
How to get fixed voltage for current mirror biasing ?
I mirr
Ucc  Uref

.N
R
I mirr
Uref

.N
R
better – doesn’t depend on Ucc
Matching hand calculation
Premise
- 2 transistors in common centroid (crossquad)
- ideal surrounding
A1
A2
A1
B1
B2
A2
B1 B2
Instructions in:
“Electrical parameters CMOS07” manual (ds13291.pdf)
Exemplary calculation – choose W/L=7  W/L= 35u/5u
quite small MOS
Matching
Error in VT0
Error in β
4
2
(I d / I d )  (VT 0 ) .

(



/

)
(VGS  VT 0 ) 2
2
2
where
2
2
(VT 0 ) 2  AVT
/
WL

C
0
VT 0
( /  ) 2  A2 / WL  C2
Statistical errors –
- count under square root
For good matching (small current difference)
- larger MOS  high WL
- higher (VGS – VT0)
Matching
Table is valid for NMOS, PMOS parameters in electrical parameters
Carefully: units
mV, μm, %
Matching
2
2
3 2
3 2
7
2
(VT 0 ) 2  AVT
/
WL

C

(
11
.
5
e
)
/(
5

35
)

(
0
.
2
e
)

7
.
957
e
V
0
VT 0
(VT 0 )  0.892 mV
( /  ) 2  A2 / WL  C2  (2.5e  2 ) 2 /(5  35)  (0.05e  2 ) 2  3.82e 6
( /  )  1.95e 3
(I d / I d ) 2  (VT 0 ) 2 .
4
2

(



/

)

2
(VGS  VT 0 )
 7.957e 7 .
4
 3.82e 6  5.47e 5
2
(0.25)
(I d / I d )  7.399e 3
I d  (I d / I d ) . I d  7.399e 3 . 20A  0.148 A
I d (cadence result )  0.1495 A
for 1 sigma
for 1 sigma
Matching
Cadence matching tool output file
Biasing currents
Usually use buffered band-gap reference voltage
1 - External resistor
- accurate resistance value, almost temperature
independent
2 – Hipo internal resistor
- hipo resistance 2000 Ω (1600 Ω - 2400 Ω)
- temperature dependence - viz. parameterFile
3 – other CMOS resistor types
- not used because of small sheet resistance
One chip can combine both types of bias currents
Biasing currents
Hipo internal resistor bias current advantages
- temperature dependent current can help with
stability of some circuits
- quite accurate voltage level shifter
U out  U ref .
R2
.N
Rbias
U out  U ref .
R2
.N  VDS _ M 2
Rbias
Current mirror and resistor MATCHING !!!!
U out  U ref .
R2
.N  U 2
Rbias
Cascoded mirror output resistance
express It it  gm4 .vgs 4 
where
it  gm4 (it .ro2 ) 
it .( gm4 .ro2 
vt  (v4 )
ro4
vgs 4  it .ro2
vt
ro
 it 2
ro4
ro4
v
ro2
 1)  t
ro4
ro4
Rocasc  gm4 .ro2 .ro4
vt
 gm4 .ro2 .ro4  ro2  ro4
it
negligible
Good luck !!!