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Standard cell layout
Topics
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Layouts for logic networks.
Channel routing.
Simulation.
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Layout made of small cells: gates, flip-flops, etc.
Cells are hand-designed.
Assembly of cells is automatic:
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Slides courtesy Modern VLSI Design, 3rd Edition
cells arranged in rows;
wires routed between (and through) cells.
Slides courtesy Modern VLSI Design, 3rd Edition
Standard cell structure
Standard cell design
pin
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VDD
Pitch: height of cell.
Feedthrough area
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pullups
n tub
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Intra-cell wiring
pulldowns
All cells have same pitch, may have different widths.
VDD, VSS connections are designed to run through cells.
A feedthrough area may allow wires to be routed over the
cell.
p tub
VSS
pin
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
Single-row layout design
Routing channels
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cell
cell
cell
cell
cell
Tracks form a grid for routing.
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Routing channel
wire
Horizontal track
Vertical track
height
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Different layers are (generally) used for horizontal and
vertical wires.
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cell
cell
Slides courtesy Modern VLSI Design, 3rd Edition
cell
cell
Spacing between tracks is center-to-center distance between
wires.
Track spacing depends on wire layer used.
Horizontal and vertical can be routed relatively independently.
cell
Slides courtesy Modern VLSI Design, 3rd Edition
Routing channel design
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Pin placement and routing
Placement of cells determines placement of pins.
Pin placement determines difficulty of routing problem.
Density: lower bound on number of horizontal tracks needed to route
the channel.
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a
Density = 3
b
c
b
c
a
Density = 2
c
Maximum number of nets crossing from one end of channel to the other.
a
a
before
Slides courtesy Modern VLSI Design, 3rd Edition
Two outputs: sum, carry.
n1
bi
ai
X1
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Generate candidates, evaluate area and speed.
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To generate a candidate:
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N1
X2
si
ci
n4
n2
bi
ci
b
Layout methodology
ai
x1
bi
c
before
Slides courtesy Modern VLSI Design, 3rd Edition
Example: full adder layout
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b
N4
N2
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ci+1
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Can improve candidate without starting from scratch.
place gates in a row;
draw wires between gates and primary inputs/outputs;
measure channel density.
ai
x2
sum
ci
N3
n3
carry
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
A candidate layout
Improvement strategies
Density = 5
a
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Swap pairs of gates.
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Exchange larger groups of cells.
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b
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x1
x2
n1
n2
n3
n4
s
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Doesn’t help here.
Swapping order of sum and carry groups doesn’t help either.
This seems to be the placement that gives the lowest
channel density.
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Cell sizes are fixed, so channel height determines area.
cout
c
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
Left-edge algorithm
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Example
Basic channel routing algorithm.
Assumes one horizontal segment per net.
Sweep pins from left to right:
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A
B
C
assign horizontal segment to lowest available track.
A
Slides courtesy Modern VLSI Design, 3rd Edition
B
C
Slides courtesy Modern VLSI Design, 3rd Edition
Limitations of left-edge algorithm
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B
Some combinations of nets require more than one
horizontal segment per net.
A
Vertical constraints
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Aligned pins form vertical constraints.
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Wire to lower pin must be on lower track; wire to upper pin must
be above lower pin’s wire.
B
A
B
B
A
?
B
A
aligned
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
Dogleg wire
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Rat’s nest plot
A dogleg wire has more than one horizontal segment.
A
B
B
A
Slides courtesy Modern VLSI Design, 3rd Edition
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Can be used to judge placement before final routing.
Slides courtesy Modern VLSI Design, 3rd Edition
Simulation
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Types of simulation
Goals of simulation:
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functional verification;
timing;
power consumption;
testability.
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Circuit simulation:
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Timing simulation:
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Gate simulation:
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Models for gate simulation:
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Example: switch simulation
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0 c
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logic gates as primitive elements.
d X
1
0X
zero delay;
unit delay;
variable delay.
1
0 c
models fault propagation (more later).
Slides courtesy Modern VLSI Design, 3rd Edition
Slides courtesy Modern VLSI Design, 3rd Edition
Example, cont’d.
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0 c
+
o
b
a
Fault simulation:
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transistors as semi-ideal switches.
Slides courtesy Modern VLSI Design, 3rd Edition
Types of simulation, cont’d.
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simple analog models to provide timing but not detailed
waveforms.
Switch simulation:
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Slides courtesy Modern VLSI Design, 3rd Edition
analog voltages and currents.
d 10
10
o
b
a
10
0 c
Slides courtesy Modern VLSI Design, 3rd Edition
10
X1