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A Multi-Mode Selectable DC-DC Converter for Ultralow Power
Circuits
Ernie Bowden, Doug Sorenson
Department of Electrical and Computer Engineering, University of Virginia
Abstract – In this paper, we implement a DC-DC
converter for usage in Ultralow Power circuits. We
use a two bit input signal to select between four
output voltages- 250mV, 500mV, 750mV, and 1V. We
implement the 250mV and 500mV outputs using a
switched-capacitor (SC) design. The 750mV is
generated using a linear regulator and the 1V is
simply passed via transmission gates from the global
VDD. We reused capacitors for the SC designs in
order to save on capacitance budget, since on-chip
capacitance consumes a lot of die area. Our
implementation results in efficiencies of up to 64%
for 250mV, 80% for 500mV, and 70% for 750mV.
I. Introduction
For most ultra-low power circuits it is highly
advantageous to allow for multiple operating
voltages.
Operating at lower voltages in the
subthreshold region allows a processor to reduce
power consumption but with the cost of decreasing
the performance of the processor. Since most
processors experience different workloads at different
periods of time, the most efficient implementation of
a design is usually one that can operate at different
voltages. It has been shown that using just three or
four different voltages and dithering between them
can attain near optimal power consumption for a
given workload [1]. It has also been shown that the
minimum energy point for many circuits can be as
low as 250mV, so therefore being able to efficiently
drop the voltage down to this value is imperative for
modern DC-DC converter designs [2]. Implementing
these voltage sources in one unit will allow us to limit
space, as on chip capacitors consume a lot of die area.
Figure 1: Quantization effect. Dashed line represents
four voltage sources with dithering. Lowest energy
line is a voltage supply with infinite output values [1]
We have implemented a DC-DC voltage
converter with a 4-way selectable output for low load
situations. We have designed the device using the 65
PTM model and ran simulations on the device using
Spectre.
In order to most closely approach the
optimal curve that models infinite output voltages we
chose the values of 250mV, 500mV, 750mV and 1V
as our target output voltages. These values give
equal spacing between outputs which helps to
approach the optimal curve when dithering is used.
II. Previous Work
A great deal of on-chip DC-DC converter
research has been performed in the last decade. The
initial method of performing DC-DC conversion was
to use a linear regulator to step down the voltage on a
chip. This method has efficiency approximately
equal to the ratio of the step down, with a 2:1 stepdown converter having an efficiency of
approximately 50%. While this method is reasonably
efficient for small voltage drops, it is not a good
solution for large voltage drop ratios.
The next method used was the buck
converter topology [3]. This method is a switchedmode power supply that uses varying duty cycles to
control the output voltage by alternating between
feeding VSS and VDD through capacitance. This
method often had on-chip capacitance but required
off chip inductance to perform filtering to get usable
voltage waveforms. The buck topology is more
efficient than linear regulators but has met limitations
as scaling has brought about smaller devices and
lower voltages.
More recent research has been focused on
switched capacitor designs where capacitors are
charged in series and then discharged in parallel,
resulting in a step-down in voltage [4]. These
designs are much higher in efficiency than previous
designs, especially when the voltages become very
low, such as in the subthreshold region. For divide
by N (N being any integer greater than 1) topologies,
the step down in the output voltage is approximately
equal to the multiplication in the output current,
resulting in theoretical efficiencies of near 100. Due
to leakage current and the amount of non-zero
frequency component that can be passed to ground
through the capacitors, this theoretical value can
never be achieved. This method is currently the most
efficient design for divide by N topologies. Another
of its key advantages over the buck topology is that it
doesn’t require inductors, so therefore the device can
be implemented completely on-chip and integrated
into the same die as the rest of the circuit. The down
side of this approach is that it doesn’t low pass filter
the output and therefore can result in a larger voltage
ripple. Some approaches have used linear regulators
to slightly step down the output of the switching
capacitor, making the device slightly less efficient but
smoothing out the output waveform [4]. Another
simple approach to reducing this ripple is to add
decoupling capacitance to the output. This minimally
decreases the efficiency but filters out much of the
high frequency ripple component.
III. Design
A. High Level Decisions
We chose our voltages in order to most
closely approximate the infinite voltage curve of
Figure 1. Using 250mV and 500mV also allowed us
to use divide by N SC topologies. As we wanted to
save die area, we decided to use the same capacitors
for each of these as we will only be allowing one
output voltage at a time. We developed a switching
system controlled by a non-overlapping clock and the
outputs of the decoder that allowed for reusing the
capacitors.
For the 750mV output we decided to use a
linear regulator with the current mirror topology.
Ramadass et al derived a maximum efficiency for
capacitive designs in a 4:3 step down case to be 75%,
and achieved a measured efficiency of approximately
74% [5]. Since this is only marginally different from
a linear regulator design we decided to use a linear
regulator for this output voltage. This allowed us to
cut down on the number of switches required in our
SC design and therefore decrease it leakage. Also, at
750mV the chip is likely to be in a computationally
intense mode and therefore have a much larger load
current than it would when operating at the lower
voltages. Using an SC design would result in larger
voltage ripples at these higher currents whereas the
linear regulator will produce a smooth output voltage.
You could increase the capacitance values and clock
frequency to lessen the ripple, but increasing the
capacitance would greatly increase the die area and
one of our goals is to keep die area to a minimum.
Since the VDD we are using for our
technology is 1V we simply passed the VDD to the
power supply’s output. We used transmission gates
as switches and the control signals coming from the
decoder to select which internal output was passed to
the global output of our device. There was a tradeoff
for sizing when deciding upon this transmission gate
size. When the gates’ sizes were small the high
voltage outputs experienced a voltage drop across the
transmission gates due to the larger loads they were
pushing. If the transmission gates were made too
large, then the leakage through them would raise the
voltages of the 250mV and 500mV outputs in low
power operation mode. We chose to use a W/L=2 for
the NMOS devices and W/L=4 for the PMOS
devices. If one were to use techniques to reduce
leakage then the W/L for the 750mV and 1V outputs
would greatly increase. To simulate our efficiencies
we assumed this case, and made the size of the
transmission gates larger when simulating the 750mV
and 1V cases.
B. Switched Capacitor Design
We allocated 80% of our self defined
transistor budget to the SC part of our design and
used the remaining 20% as decoupling capacitance
on the output. We broke the SC budget down into
four equal capacitance transistors, allowing us to set
up both divide by four and divide by two topologies.
For the divide by two we connected the four
capacitors into two pairs. We used transmission
gates for the switches, with a W/L=2 for the PMOS
and W/L=1 for the NMOS. These small gates
allowed us to minimize leakage, and since the current
draw is low for the low voltage, the IR drop across
our transmission gates is still minimal. A schematic
of our design follows.
Clock1
Vdd=1V
Clock1
OR D1
Clock2
AND D0
Clock2
AND D0
Clock2
AND D1
Clock1
Clock2
AND D0
Clock2
AND D0
V1
Clock2
AND D1
Clock2
AND D0
Clock1
OR D1
Clock2
AND D0
V0
Figure 2: Switched Capacitor Circuit
C. Linear Regulator
For our linear regulator we used a typical
current mirror type design. For simplification we use
an ideal model of a current source for the current
mirror but since this current source is small compared
to the load current this voltage output will be
operating with, the ideal model is a close enough
approximation. A schematic of our design follows:
Figure 3: Linear Regulator Circuit
VT logic and made large, so that they have a low on
resistance as well as low leakage.
IV. Results
A. Smal Load Output Voltages
The first thing we tested was to see that our
low load voltages were at the desired levels. We also
used this analysis to determine the voltage ripple.
We tested the design with and without a 10pF
decoupling capacitor on the output.
With the
decoupling capacitor the voltage ripple was
drastically reduced, being much less than a mV, so
we decided to use this for all our voltage levels. This
will also help get rid of noise in the power supply.
This decoupling capacitance was only 20% of our
transistor budget and greatly improved the ripple and
noise resiliency. We ran the circuit with low load
impedance and give the results below:
D. Selector
We take as an input to our circuit a two bit
data string that selects the operating voltage of our
power supply.
We implemented a two-to-four
decoder to take these inputs and generate the four
control signals (D0…D3) and their complements. D0
and D1 are used in the SC design and all the control
signals are used to select which internal output
becomes the global voltage output of our power
supply. The select logic follows:
Figure 5: Small Load Output Voltages
Figure 4: Output Selection Logic
This is the portion of our circuit that needs
to be especially protected from leakage current.
When V0 or V1 is selected and the load current is
small, having large transmission gates leads to a
significant amount of leakage current from VDD and
the linear regulator compared to the amount of
current drawn by the low power circuit, therefore
increasing the voltage of V0 and V1. When VDD or
the output of the linear regulator is selected and the
load current is large, there is a voltage drop across the
resistance of the small gates. In future work, these
transmission gates should be implemented in High-
B. Effects of Different Capacitor Sizes
We studied the effects of different capacitor
sizes. We ran simulations using both 10pF and 20pF
for each capacitor. Using the larger capacitors
resulted in a larger charge and discharge time when
switching between different output values as well as
greatly increasing the die area. The benefit of larger
capacitance is that for large load currents, larger
capacitors result in higher efficiencies. Sizing the
capacitors is therefore dependent upon the load
current your circuit is designed to power. If you wish
to switch quickly between voltage states you must
take into account the energy used when charging and
discharging the capacitors when you are calculating
your power efficiency, with larger capacitors more
dramatically increasing efficiency in this way.
C. Efficiency Calculations
We ran simulations with varying load
currents to determine the efficiency of our design.
We did this for both 10pF and 20pF capacitance
values for the 250mVand 500mV cases. We found
that for low currents the 10pF case actually had a
slightly higher efficiency than the 20pF case but this
reversed for larger load currents, with the 20pF case
being the most efficient. Since we are designing for
an Ultralow Power circuit, the 10pF values work best
for us, especially in the load range of a few
microamps. Graphs for the 250mV and 500mV
designs are listed below.
D. Effects of Load Current on Output Voltage
As the load current goes up for switched
capacitor designs the voltage produced goes down.
The larger the capacitance you use, the less the
voltage drops for a given load current. You can also
increase the switching frequency of the clock driving
the SC circuit, such as in dynamic frequency scaling
[5]. With dithering we can move between the
different output voltages so changes in output voltage
will result in slight movement of the four points we
are creating on the energy curve and therefore only
minimally affecting the overall power dissipation of
the circuit This allows us to continue to use the small
capacitors to save room and allow for high efficiency
at very low power draw. A graph showing the
voltage as the load current is swept follows:
Figure 8: Effect of Changing Load Current on Output
Voltage
Figures 6 & 7: Efficiency Curves for Low Output
Currents
For the 750mV output, we calculated an
efficiency of approximately 70% for output currents
in the milliamp range. The current in was very close
to the current out and the efficiency is therefore
approximately
(Vout / Vin)  ( Isrc / Iload ) .
For Iload much larger than Isrc (36.2 microamps in
our implementation) the efficiency approaches Vout
divided by Vin. At this step down ratio, this method
is therefore close to SC designs in efficiency if there
is a significantly large load current, which we are
assuming in this operation mode. There is some
leakage across gates but it is minimal since none of
the transistors are off in the linear regulator.
For the 1V output case we simply are
passing VDD through a transmission gate. Assuming
proper sizing of transmission gates this efficiency
will be very near 100%.
V. Conclusions
We developed a completely on-chip
selectable output DC-DC converter using both a
linear regulator and a shared switched capacitor
design. The circuit was simulated in the 65 nm PTM
technology using Spectre. We achieved maximum
efficiencies of 64% for the 250mV output, 80% for
the 500mV output, 70% for 750mV output, and near
100% for the 1V output. This circuit can allow for an
Ultralow Power circuit to switch between multiple
operational voltages efficiently. This is especially
important for devices that have different levels of
computational complexity at different times, such as
wireless sensor nodes. The capacitors in our design
are very small, using only 50pF of total capacitance.
This is much smaller than the values used in previous
works, such as 200pF or 2.4nF, and will result in
greatly reduced die area compared to these designs
[4,5]. It is specifically designed to be efficient down
to less than a microamp, though it can be adapted for
larger loads by increasing the capacitance values and
the clock frequency.
References
[1]
[2]
V. Gutnik and A. Chandrakasan, “Embedded
Power Supply for Low-Power DSP”, IEEE
Transactions on Very Large Scale
Integration (VLSI) Systems,
December
1997, Vol. 5, No. 4,
pp 425-436
B. Calhoun, and A. Chandrakasan,
“Characterizing and Modeling Minimum
Energy
Operation
for
Subthreshold
Circuits”, 2004 International Symposium on
Low Power Electronics and Design,
Proceedings of, pp.90-95
[3]
S. Reynolds, “A DC-DC Converter for
Short-Channel CMOS Technologies”, IEEE
Journal of Solid-State Circuits, Vol. 32, no.
1, Jan. 1997
[4]
T. Hirose, T. Asai, and Y. Amemiya, “PowerSupply Circuits
for
Ultralow-Power
Subthreshold
MOS-LSIs”,
IEICE
Electronics Express, 2006, Vol.3, No. 22, pp.
464-468
[5]
Y. K. Ramadass and A. P. Chandrakasan,
“Voltage Scalable Switched Capacitor DCDC Converter for Ultra-Low-Power OnChip Applications”, Power Electronics
Specialists Conference, IEEE PESC 2007
Record, Vol. 1, pp. 2353-2359