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AD8226
运算放大器 spec
Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier
FEATURES
Gain set with 1 external resistor
Gain range: 1 to 1000
Input voltage goes below ground Inputs protected beyond supplies Very wide power
supply range Single supply: 2.2 V to 36 V Dual supplies: ±1.35 V to ±18 V Bandwidth
(G = 1): 1.5 MHz
CMRR (G = 1): 90 dB minimum for BR models Input noise: 22 nV/√Hz
Typical supply current: 350 μA
Specified temperature: ?40°C to
APPLICATIONS
125°C 8-lead SOIC and MSOP packages
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Industrial process controls Bridge amplifiers
Medical instrumentation Portable data acquisition Multichannel systems
GENERAL DESCRIPTION
The AD8226 is a low cost, wide supply range instrumentation
amplifier that requires only one external resistor to set any gain between 1 and 1000.
The
AD8226
is
designed
to
work
with
a
variety
http://www.wendangwang.com/doc/b26aead8710c46420b4b74cevoltages.
of
A
wide
signal
input
range and rail-to-rail output allow the signal to make full use of the supply rails.
Because the input range also includes the ability to go below the negative supply,
small signals near ground can be amplified without requiring dual supplies. The AD8226
operates on supplies ranging from ±1.35 V to ±18 V for dual supplies and 2.2 V to
36 V for single supply.
The robust AD8226 inputs are designed to connect to
real-world sensors. In addition to its wide operating range, the
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its
use. Specifications subject to change without notice. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.
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Tradehttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cemarks and registered
trademarks are the property of their respective owners.
AD8226
PIN CONFIGURATION
–IN
VSRGVOUTRGREF IN
–VS
1
0TOP VIEW0-6(Not to Scale)
3070
Figure 1.
Table 1. Instrumentation Amplifiers by Category1
General
Zero
Military
Low
High Speed Purpose Drift Grade Power PGA
AD8220AD8231AD620AD627AD8250AD8221AD8290AD621AD623AD8251AD8222AD8293AD524AD8223A
D8253AD8224AD8553AD526AD8228AD8556AD624AD8227 AD8295
AD8557
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1
Visit www.analog.com for the latest instrumentation amplifiers.
AD8226 can handle voltages beyond the rails. For example,
part is guaranteed to withstand ±35 V
with a ±5 V supply, the
at the input with no damage. Minimum as well
as maximum input bias currents are specified to facilitate open wire detection. The
AD8226
is
perfect
for
multichannel,
spahttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cece-constrained
industrial applications. Unlike other low cost, low power instrumentation amplifiers,
the AD8226 is designed with
a minimum gain of 1 and can easily handle ±10 V signals.
With its MSOP package and 125°C temperature rating, the AD8226 thrives in tightly
packed, zero airflow designs.
The AD8226 is available in 8-lead MSOP and SOIC
packages, and is fully specified for ?40°C to
125°C operation. For a device with
a similar package and performance as the AD8226 but with gain settable from 5 to 1000,
consider using the AD8227.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700
www.analog.com Fax: 781.461.3113 ?2009 Analog Devices, Inc. All rights reserved.
AD8226
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Gain
Selection ......................................................................
.......
19
Reference
Terminal ......................................................http://www.wendan
gwang.com/doc/b26aead8710c46420b4b74ce..............
Range
20
Input
Voltage
...................................................................
20
Layout .........................................................................
.................
Path
20
Input
Bias
...............................................
Current
21
Return
Input
Protection .....................................................................
.... 22 Radio Frequency Interference (RFI) ........................................
22
Information
Applications
..............................................................
23
Differential
Drive ....................................................................... 23
Precision
Strain
Gage ................................................................. 24 Driving
an ADC .........................................................................
24
Outline
Dimensions .....................................................................
..
25
Ordering
Guide ...http://www.wendangwang.com/doc/b26aead8710c46420b4b74ce................
....................................................... 25
TABLE OF CONTENTS
Features .......................................................................
.......................
1
Applications ...................................................................
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....................
1
Pin
Configuration ..................................................................
...........
1
General
Description ....................................................................
.....
1
Revision
History ........................................................................
.......
2
Specifications .................................................................
....................
3
Absolute
Maximum
Ratings ............................................................ 7 Thermal
Resistance ......................................................................
7
ESD
Caution ....................................http://www.wendangwang.com/doc/b26ae
ad8710c46420b4b74ce..............................................
7
Pin
Configuration and Function Descriptions ............................. 8 Typical
Performance Characteristics ............................................. 9 Theory
of
Operation ......................................................................
19
Architecture ...................................................................
.............. 19
REVISION HISTORY
7/09—Rev. 0 to Rev. A
Added BRZ and BRM Models .......................................... Universal
Changes
to
Features
Section............................................................ 1 Changes to
Table
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1 ............................................................................ 1
Changes to General Description Section ...................................... 1
Changes to Gain vs. Temperature Parameter, Output Parameter,
and Operating Range
Parameter,
Table
2 ..............................http://www.wendangwang.com/doc/b26aead8710c46420
b4b74ce........... 4 Changes to Common-Mode Rejection Ratio (CMRR) Parameter
to Input Offset, VOSO, Average Temperature Coefficient
3
and
Parameter, Table
........................................................................
5
Changes to Gain vs. Temperature Parameter, Table 3 ................. 6 Changes to
Gain Selection Section ............................................... 19 Changes
to Reference Terminal Section and Input Voltage
Range
Section ........................................................................
......
Guide
20
Changes
to
..........................................................
Ordering
25
1/09—Revision 0: Initial Version
Rev. A | Page 2 of 28
H
AD8226
SPECIFICATIONS
VS =
15 V, ?VS = ?15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications
referred to input, unless otherwise noted. Table 2.
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ARZ,
ARMZ
BRZ,
BRMZ
Typ
Max
Min
Typhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ce Max Unit COMMON-MODE
REJECTION RATIO (CMRR) VCM = ?10 V to
= 1
80
90
dB G = 10
100
105
dB CMRR with DC at 5 kHz
90
dB G = 1000
100
100
10 V
CMRR with DC to 60 Hz
dB G = 100
G = 1 80
105
80
110
dB G = 10
dB G = 1000
90
90
G
105
dB G = 100
110
90
dB
22
NOISE Total noise: eN = √(eNI
(eNO/G)
Voltage Noise
Input Voltage Noise, eNI Output Voltage Noise, eNORTI
G = 1 G = 10 G = 100 to 1000 Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Average Temperature Coefficient Output Offset, VOSO
Average Temperature Coefficient Offset RTI vs. Supply (PSR) G = 1 G = 10 G = 100 G
= 1000 INPUT CURRENT Input Bias Current1
Average Temperature Coefficient Input Offset Current
Average Temperature Coefficient REFERENCE INPUT RIN IIN Voltage Range
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Reference
Gain
to
Output
Reference
Gaihttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cen
Error
DYNAMIC
RESPONSE Small-Signal ?3 dB Bandwidth G = 1
G = 10 G = 100 G = 1000
1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz Total offset voltage:
VOS = VOSI
(VOSO/G) VS = ±5 V to ±15
V TA = ?40°C to
125°C VS = ±5 V to ±15 V TA = ?40°C to
±15 V
25°C TA =
TA =
TA =
2
125°C TA = ?40°C TA = ?40°C to
125°C TA = ?40°C TA = ?40°C to
22
22 nV/√z
2 μV p-p
p-p
120
0.5
80
200
90
dB 100
nA 5 30 5 30 nA
100 kΩ
1500
7
125°C VS = ±5 V to
125°C TA =
25°C
fA/√Hz
3
125°C
120 nV/√z
0.5 μV p-p
100 μV
105
70
7 μA ?VS
kHz
0.5 2
dB 105
70
0.4
μV p-p
0.5 1 μV/°C
110
pA/°C
VSS
0.4
dB 105
nA
VS 1
1
160
1000
110
nA
V/V
100
0.01
100
500 μV
dB
nA
pA
1 5 μV/°C
5 20 5 20 nA 5 15 5 15
5
0.01
160
2 10
3
5
pA/°C
%
100
1500
kz
20
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http://www.wendangwang.com/doc/b26aead8710c46420b4b74ce20 kz
2
2
kHz
Rev. A | Page 3 of 28
AD8226
ARZ, ARMZ BRZ, BRMZ
= 1
25
Typ Max Min Typ Max Unit Settling Time 0.01% 10 V step
25 μs G = 10
Slew Rate G = 1
kΩ/RG)
0.4
15
0.4
Gain Range
5 to 1000
0.3
RL ≥ 2 kΩ
15 μs G = 100
V/μs
1
1
40
G = 5 to 100
0.6
40 μs G = 1000
0.6
350
350 μs
V/μs GAIN G = 1
V/V Gain Error VOUT ±10 V
0.1 % Gain Nonlinearity VOUT = ?10 V to
ppm G = 100 RL ≥ 2 kΩ
G
(49.4
G = 1
% G =
10 V
G = 1 to 10
ppm G = 1000 RL ≥ 2 kΩ
ppm
2
Gain vs. Temperature
to 125°C
5
±1.35 V to
G = 1 TA = ?40°C to
2 ppm/°C G > 1 TA = ?40°C to
36 V
85°C
125°C
Input Impedance
GΩ||pF Common Mode
0.4||2
5
1 ppm/°C
?100
Differential
TA = 85°C
?100 ppm/°C S =
0.8||2
0.8||2
0.4||2 GΩ||pF
3
Input Operating Voltage RangeTA =
25°C ?VS ? 0.1
VS ? 0.8 ?VS ? 0.1
VShttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ce
125°C ?VS ? 0.05
0.9 ?VS ? 0.15
40
?VS
40
VS ? 40
TA =
125°C ?VS
1.2
VS ? 0.6 V
0.8
0.4
?VS
40 V OUTPUT
25°C ?VS
VS – 1.0 ?VS
0.4
0.4
Output Swing
VS ? 0.7 ?VS
VS – 1.0 V
VS – 1.1 V RL = 10 kΩ to Ground
V
TA
TA = ?40°C ?VS ? 0.15
VS ? 0.9 V Input Overvoltage Range TA = ?40°C to
Ground
1.1 ?VS
VS ? 0.6 ?VS ? 0.05
?
125°C
VS ?
VS ?
RL = 2 kΩ to
0.4
VS ? 0.7 V
TA = ?40°C ?VS
TA =
=
25°C ?VS
1.2
0.2
TA =
VS –
VS ?
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0.2 ?VS
V
0.2
VS ? 0.2 V
TA = ?40°C ?VS
TA = ?40°C to
Current
±1.35
13
0.2
TA =
VS ? 0.2 ?VS
125°C ?VS
0.1
85°C
0.3
0.2
VS ? 0.3 ?VS
0.1
Operating Range Dual-supply operation ±1.35
25°C
450
?40
?40
VS ? 0.3
VS ? 0.1 V Short-Circuit
350
350 μA
450
TA = ?40°C
250
μA
125°Chttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ce
TEMPERATURE RANGE
0.3
VS ? 0.2 V RL = 100 kΩ to Ground
VS ? 0.1 ?VS
13 mA POWER SUPPLY
V Quiescent Current TA =
=
125°C ?VS
250 μA
TA
525
525
TA
=
μA
°C
The input stage uses pnp transistors; therefore, input bias current always flows into
the part.
The values specified for G > 1 do not include the effects of the external
gain-setting resistor, RG. 3
Input voltage range of the AD8226 input stage. The input range depends on the
common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
12
Rev. A | Page 4 of 28
HHAD8226
VS = 2.7 V, ?VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications
referred to input, unless otherwise noted. Table 3.
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Parameter
COMMON-MODE REJECTION RATIO (CMRR) CMRR with DC to 60 Hz
G = 1 G = 10 G = 100 G =
1000 CMRR with DC at 5 kHz G = 1 G = 10 G = 100 G = 1000 NOISE
Voltage Noise
Input
Voltage
Noise,
eNI
Outpuhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cet Voltage Noise, eNO
RTI
G = 1 G = 10 G = 100 to 1000 Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Average Temperature Coefficient Output Offset, VOSO
Average Temperature Coefficient Offset RTI vs. Supply (PSR) G = 1 G = 10 G = 100 G
= 1000 INPUT CURRENT Input Bias Current1
Average Temperature Coefficient Input Offset Current
Average Temperature Coefficient REFERENCE INPUT RIN IIN Voltage Range
Reference Gain to Output Reference Gain Error DYNAMIC RESPONSE Small-Signal ?3 dB
Bandwidth G = 1
G = 10 G = 100 G = 1000
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ARZ, ARMZ BRZ, BRMZ
Conditions Min Typ VCM = 0 V to 1.7 V
105
110
dB
100
100
dB Total noise: eN = √(eNI2
1 kHz
105
22
110
80
dB
22 nV/√z
80
120
80
dB
90
90
dB
90
100
dB
105
dB
90
dB
90
(eNO/G2
120 nV/√z f = 0.1 Hz to 10 Hz
2.0
http://www.wendangwang.com/doc/b26aead8710c46420b4b74ce 2.0 μV p-p
0.5
0.5 μV p-p
10 Hz
3
= ?40°C to
3
0.4
0.4
μV p-p f = 1 kHz
110
125°C 0.5 2
dB
TA =
5 30 5 30 nA TA = ?40°C to
nA TA = ?40°C
7 μA
kHz
?VS
160
100
pA p-p Total offset voltage: VOS = VOSI
0.5 1 μV/°C
5 μV/°C VS = 0 V to 1.7 V
105
100
80
nA TA =?40°C to
VSS
160 kz
VS
1
1
20
20 kz
V/V
2
70
90
70
125°C
0.01
(VOSO
μV TA
μV TA = ?40°C to
dB
25°C 5 20 5 20 nA TA =
125°C
fA/√Hz f = 0.1 Hz to
100
5
0.01
dB
105
2 10 1
110
dB
125°C 5 15 5 15 nA TA = ?40°C
pA/°C TA =
5
105
125°C
25°C
pA/°C
nA TA =
100
%
125°C
100 kΩ
1500
7
1500
2 kz
Rev. A | Page 5 of 28
AD8226
Parameter Conditions Settling Time 0.01% 2 V step G = 1
Slew Rate G = 1
G = 5 to 100 GAIN G = 1
G = 10
G = 100
(49.4 kΩ/RG) Gain Range
G = 1000
Gain Error
G
= 1 VOUT = 0.8 V to 1.8 V http://www.wendangwang.com/doc/b26aead8710c46420b4b74ceG
= 5 to 1000 VOUT = 0.2 V to 2.5 V
2
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Gain vs. Temperature G = 1 TA = ?40°C to
= ?40°C to
S = 0 V,
85°C
TA =
85°C to
125°C G > 1 TA
125°C
VS = 2.7 V to 36 V Input Impedance
Differential
Common Mode
TA = ?40°C
TA =
3
Input Operating Voltage RangeTA =
Overvoltage Range TA = ?40°C to
25°C
125°C Input
125°C OUTPUT
ARZ, ARMZ BRZ, BRMZ
Min Typ
0.6
6
0.6
V/μs
1 ppm/°C
0.4||2
5
VS ? 0.1
0.1
VS ? 0.1
V
6
6 μs
1
1
V/V
2 ppm/°C
0.4||2 GΩ||pF ?0.1
0.9 V ?0.05
0.1
6 μs
VS ? 0.6 ?0.05
?100
35
35 μs
0.04
350
350 μs
0.01% %
0.3
ppm/°C
VS ? 0.7 ?0.1
VS ? 0.6 V
0.4
0.1% %
0.8||2
VS ? 0.7 V ?0.15
VS ? 40
?VS
0.4
5
0.8||2 GΩ||pF
VS ? 0.9 ?0.15
40
V/μs
VS ? 40
?VS
VS ?
40
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Output Swing
Short-Circuit Curhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cerent
POWER SUPPLY Operating Range Quiescent Current
TEMPERATURE RANGE
12
RL = 10 kΩ to 1.35 V,
TA = ?40°C to
125°C
Single-supply operation
TA =
25°C, ?VS = 0 V,
= 0 V,
13
500
VS = 2.7 V TA = ?40°C, ?VS = 0 V,
VS = 2.7 V TA =
13 mA
2.2
425 500 μA
125°C, ?VS = 0 V,
36 2.2
475 550
36 V
325 400
475 550 μA ?40
VS = 2.7 V TA =
85°C, ?VS
VS = 2.7 V
325 400 μA
?40
250 325
250 325 μA
425
°C
Input stage uses pnp transistors; therefore, input bias current always flows into
the part.
The values specified for G > 1 do not include the effects of the external gain-setting
resistor, RG. 3
Input voltage range of the AD8226 input stage. The input range depends on the
common-mode voltage, the differential voltage, the gain, and the reference voltage.
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See the Input Voltage Range section for more information.
http://www.wendangwang.com/doc/b26aead8710c46420b4b74ceRev. A | Page 6 of 28
AD8226
THERMAL RESISTANCE
ABSOLUTE MAXIMUM RATINGS
Table 4.
θJA is specified for a device in free air. Supply Voltage ±18 V Table 5. Thermal
Resistance Output Short-Circuit Current Indefinite JAMaximum Voltage at ?IN or
IN ?VS
IN
40 V 8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W Minimum Voltage at ?IN or
VS ? 40 V 8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W REF Voltage ±VS
Storage Temperature Range ?65°C to
150°C
ESD CAUTION Specified Temperature Range ?40°C to
Maximum Junction Temperature 140°C
Human Body Model 1.5 kV Charge Device Model 1.5 kV
125°C
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Machine Model 100 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage
to the device. This is a stress rating only; functional operation of the device at
these
or
any
other
conditions
above
those
indicated
ihttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cen the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Rev. A | Page 7 of 28
AD8226
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN
RGRG IN
VSVOUTREF–VS
07036-002
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TOP VIEW(Not to Scale)
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description Negative Input. 2, 3 RG Gain-Setting Pins. Place a gain
resistor between these two pins. 4
IN Positive Input.
SSupply. 6 REF Reference.
This pin must be driven by low impedance. OUT SSupply.
Rev. A | Page 8 of 28
AD8226
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.
S
Thttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ceIH1
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–900–600
–30003006009003
0-63V0OSO @ ±15V (?V)
70Figure 3. Typical Distribution of Output Offset Voltage
S
TIH2
–9–6
–3036930-63V0OSO DRIFT (?V)
70Figure 4. Typical Distribution of Output Offset Voltage Drift
S
TIH3
–400
–200
020040030-63V0OSI @ RG PINS @
±15V (?V)
70Figure 5. Typical Distribution of Input Offset Voltage
250
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200
S
150
TIH100
4
–1.2
–0.9–0.6
–0.3
00.30.60.91.2
30-63V0OSI DRIFT (?V)
70Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100
180
150
120
S
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TIH5
18
202224
26
30-63POSITIVE I0BIAS CURRENT @ ±15V
(nA)
70Figure 7. Typical Distribution of Input Bias Current
300://www.wendangwang.com/doc/b26aead8710c46420b4b74cepar
250
200
S
TIH150
100
506–0.9–0.6
–0.300.30.60.9
30-63V0OSI @ ±15V (nA)
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70Figure 8. Typical Distribution of Input Offset Current
Rev. A | Page 9 of 28
AD8226
2.5
2.5
2.0
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
2.0
1.5
1.5
1.0
0.5
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1.0
0.50–0.5–1.0–0.5
00.5
2.01.01.5
OUTPUT VOLTAGE (V)
2.53.0
–0.5–0.5
00.5
2.01.0
1.5
OUTPUT VOLTAGE (V)
2.53.0
Figure 9. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS =
2.7 V, G = 1
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
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Single Supply, VS =
2.7 V, G = 100
5
5
COMMON-MODE VOLTAGE (V)://www.wendangwang.com/doc/b26aead8710c46420b4b74cer
COMMON-MODE VOLTAGE (V)
44
3
3
2
2
11
–1–0.5
00.51.0
1.52.02.53.03.5OUTPUT VOLTAGE (V)
4.04.55.05.5
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–1–0.5
00.51.0
1.52.02.53.03.5OUTPUT VOLTAGE (V)
4.04.55.05.5
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS =
5 V, G = 1 Figure 13. Input Common-Mode Voltage vs. Output
Voltage,
Single Supply, VS =
5 V, G = 100
6
6
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
44
2
2
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00
–2
–2
–4
–4
–6–6
–4
–202OUTPUT VOLTAGE (V)
46
–6–6
–4
–202OUTPUT VOLTAGE (V)
46
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
Dual
Supplies,
VS
=
±5
V,
Fighttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ceure
G
=
14.
1
Input
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Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±5 V, G = 100
Rev. A | Page 10 of 28
2015COMMON-MODE VOLTAGE (V)
AD8226
20
COMMON-MODE VOLTAGE (V)
151050–5–10–15
1050–5–10–15
–20–20
–15–10
5–50
OUTPUT VOLTAGE (V)
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101520
–20–20
–15–10
5–50
OUTPUT VOLTAGE (V)
101520
Figure 15. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±15 V, G = 1
Figure 18. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS
= ±15 V, G = 100
OUTPUT VOLTAGE (V)
0.6
0.50.40.3
0.60.5
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0.40.30.20.10
OUTPUT VOLTAGE (V)
INPUT CURRENT (mA)
0.20.10
–0.1–0.2–0.3–0.4–0.5
–0.1–0.2–0.3–0.4–0.5
07http://www.wendangwang.com/doc/b26aead8710c46420b4b74ce036-044
Figure 16. Input Overvoltage Performance, G = 1, VS = 2.7 V
Figure 19. Input Overvoltage Performance, G = 100, VS = 2.7 V
OUTPUT VOLTAGE (V)
0.5
0.40.3
INPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
0.6
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0.50.40.30.20.1
0–0.1–0.2–0.3–0.4–0.5
07036-048
0.10–0.1–0.2–0.3–0.4
Figure 17. Input Overvoltage Performance, G = 1, VS = ±15 V
07036-04
5
–0.5–40–35–30–25–20–15–10–50510152025303540
INPUT VOLTAGE (V)–0.6–40–35–30–25–20–15–10–50510152025303540
INPUT VOLTAGE (V)
Figure 20. Input Overvoltage Performance, G = 100, VS = ±15 V
Rev. A | Page 11 of 28
INPUT CURRENT (mA)
0.2
07036-047
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–0.6–40–35–30–25–20–15–10–50510152025303540
INPUT VOLTAGE (V)–0.6–40–35–30–25–20–15–10–50510152025303540
INPUT VOLTAGE (V)
://www.wendangwang.com/doc/b26aead8710c46420b4b74cearINPUT CURRENT (mA)
AD8226
302928INPUT BIAS CURRENT (nA)
NEGATIVE PSRR (dB)
07036-04
9
2726252423222120191817
16–0.5
0.5
1.01.52.02.53.03.5COMMON-MODE VOLTAGE (V)
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4.04.5110
1001kFREQUENCY (Hz)
10k100k1M
Figure 21. Input Bias Current vs. Common-Mode Voltage, VS =
PSRR vs. Frequency
504540INPUT BIAS CURRENT (nA)
35302520151050
07036-05
GAIN (dB)
–12
–8–4048COMMON-MODE VOLTAGE (V)
12161k
10k100kFREQUENCY (Hz)
1M10M
5 V Figure 24. Negative
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Figure 22. Input Bias Current vs. Common-Mode Voltage, VS = ±15 V
Figure 25. Gain vs. Frequency, VS = ±15 V
POSITIVE PSRR (dB)
GAIN (dB)
07036-013
110
1001kFREQUENCY (Hz)
10k100k1M1k
://www.wendangwang.com/doc/b26aead8710c46420b4b74cepar10k100kFREQUENCY (Hz)
1M10M
Figure 23. Positive PSRR vs. Frequency, RTI
Figure 26. Gain vs. Frequency, 2.7 V Single Supply
Rev. A | Page 12 of 28
07036-016
0.1100
07036-01
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5
–5–16100
07036-01
4
0.1
160
140AD8226
125150
INPUT BIAS CURRENT (nA)
120100
100
07036-017
75
50
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25
110
1001k
FREQUENCY (Hz)
10k100k0
1530456075TEMPERATURE (°C)
90
Figure 27. CMRR vs. Frequency, RTI Figure 30. Input Bias Current and Input Offset
Current vs. Temperature
120
100
20
10GAIN ERROR (?V/V)
–10–20–30–40–50
CMRR (dB)
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–60
07036-018
07036-05107036-052
0.1
110
1001k
FREQhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ceUENCY (Hz)
10k100k
–70
–60–40–20020406080
TEMPERATURE (°C)
100120140
Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
vs. Temperature, G = 1
3.0CHANGE IN INPUT OFFSET VOLTAGE (?V)
2.52.01.51.00.50–0.5–1.0–1.5–2.0–2.5
Figure 31. Gain Error
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07036-011
20
10
CMRR (?V/V)
–10–20
–30
10
20
30
405060708090WARM-UP TIME (Seconds)
100110120
–3.0
–40–50
–30–10
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10305070TEMPERATURE (°C)
90110130
Figure 29. Change in Input Offset Voltage vs. Warm-Up Time
Figure 32. CMRR vs. Temperature, G = 1
Rev. A | Page 13 of 28
07036-01
2
0.1–45–30–150
105120135
INPUT OFFSET CURRENT (pA)
CMRR (dB)
AD8226
V
://www.wendangwang.com/doc/b26aead8710c46420b4b74cepar
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INPUT VOLTAGE (V)REFERRED TO SUPPLY VOLTAGES
OUTPUT VOLTAGE SWING (V)
–V07036-053
246
81012SUPPLY VOLTAGE (±VS)
141618
1k10kLOAD RESISTANCE (?)
100k
07036-056
100
Figure 33. Input Voltage Limit vs. Supply Voltage Figure 36. Output Voltage Swing
vs. Load Resistance
V
V
–0.2
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OUTPUT VOLTAGE SWING (V)REFERRED TO SUPPLY VOLTAGES
OUTPUT VOLTAGE SWING (V)REFERRED TO SUPPLY VOLTAGES
07036-054
–0.4–0.6–0.8
–V2
4
6
81012SUPPLY VOLTAGE (±VS)
14
16
18
100?1MOUTPUT CURRENT (A)
10M
07036-057
–V10?
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Figure 34. Output Voltage Swing vs. Supply Voltage, RL
= 10 kΩ Figure 37. Output Voltage Swing vs. Output Current, G = 1
V86
G = 1
OUTPUhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ceT
(V)REFERRED TO SUPPLY VOLTAGES
NONLINEARITY (2ppm/DIV)
–V420–2–4–6
07036-05
5
SUPPLY VOLTAGE (±VS)
–8–6–4
–2024OUTPUT VOLTAGE (V)
6810
07036-019
VOLTAGE
SWING
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–8–10
Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ Figure 38. Gain
Nonlinearity, G = 1, RL ≥ 2 kΩ
Rev. A | Page 14 of 28
8
6
AD8226
NONLINEARITY (2ppm/DIV)
420–2–4–6
07036-02
NOISE (nz)
–8–6–4
–2024OUTPUT VOLTAGE (V)
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6810
FREQUENCY (Hz)
Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ
Figure 42. Voltage Noise Spectral Density vs. Frequency
NONLINEARITY (20ppm/DIV)
07036-02
4
07036-021
–10
–8–6–4
–2024OUTPUT VOLTAGE (V)
6810http://www.wendangwang.com/doc/b26aead8710c46420b4b74ce
Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ
Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000
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NONLINEARITY (100ppm/DIV)
1k
NOISE (fz)
–200–400–600
07036-022
100
–8–6–4
–2024OUTPUT VOLTAGE (V)
6810110
100
FREQUENCY (Hz)
1k10k
Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ
Figure 44. Current Noise Spectral Density vs. Frequency
Rev. A | Page 15 of 28
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07036-058
–800
–10
10
07036–8–10
AD8226
5
2
0-63070
Figure 45. 0.1 Hz to 10 Hz Current Noise
302724)
p-p
21(V E18AGTL15VO TU12PTU9O630100
1k
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10k
100k1M
FREQUENCY (Hz)
Figure 46. Large-Signal Frequency Response
60-63070
http://www.wendangwang.com/doc/b26aead8710c46420b4b74ceFigure
47.
Pulse Response and Settling Time,
G = 1, 10 V Step, VS = ±15 V
1
60-63070Figure 48. Large-Signal Pulse Response and Settling Time,
G = 10, 10 V Step, VS = ±15 V
2
60-63070
Figure 49. Large-Signal Pulse Response and Settling Time,
Large-Signal
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G = 100, 10 V Step, VS = ±15 V
3
60-63070Figure 50. Large-Signal Pulse Response and Settling Time,
G = 1000, 10 V Step, VS = ±15 V
Rev. A | Page 16 of 28
6
20-63070
Figure 51. Small-Signal Response, G = 1, RL = 10 kΩ, CL = 100 pF
20-6307
Figure 52. Small-Signal Response, G = 10, RL = 10 kΩ, CL = 100 pF
AD8226
820-6307
7
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Figure 53. Small-Signal Response, G = 100, RL = 10 kΩ, CL = 100 pF
9
20-63070
Figure
54.
Small-Signal
Reshttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ceponse, G = 1000, RL = 10
kΩ, CL = 100 pF
Rev. A | Page 17 of 28
AD8226
30-63070
Figure 55. Small-Signal Response with Various Capacitive Loads,
G = 1, RL = ∞
60
50
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)
s?40
( EMIT 30
NGILTTSE20
10
4
60-6300702
4
6
8
101214
16
18
20
STEP SIZE (V)
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Figure 56. Settling Time vs. Step Size, VS = ±15 V Dual Supplies
340
330
)
A?( TN320
RERUC Y
L310
PUPS300
290
6
024
681012141618
60-63SUPPLY VOLTAGE (±V0S)
70Figure 57. Supply Current vs. Supply Voltage
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Rev. A | Page 18 of 28
AD8226
S
GAIN STAGE
AMPLIFIER STAGE
07036-003
://www.wendangwang.com/doc/b26aead8710c46420b4b74ceTHEORY OF OPERATION
OUT
Figure 58. Simplified Schematic
ARCHITECTURE
The AD8226 is based on the classic 3-op-amp topology. This topology has two stages:
a preamplifier to provide differential amplification, followed by a difference
amplifier to remove the common-mode voltage. Figure 58 shows a simplified schematic
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of the AD8226.
The first stage works as follows: in order to maintain a constant voltage across the
bias resistor RB, A1 must keep Node 3 a con-stant diode drop above the positive input
voltage. Similarly, A2 keeps Node 4 at a constant diode drop above the negative input
voltage. Therefore, a replica of the differential input voltage is placed across the
gain-setting resistor, RG. The current that
flow through the R1
the
flows across this resistance must also
and R2 resistors, creating a gained differential signal between
A2
and
A1
outputs.
Note
that,
http://www.wendangwang.com/doc/b26aead8710c46420b4b74cein addition to a gained
differential signal, the original common-mode signal, shifted
a diode drop up, is
also still present.
The second stage is a difference amplifier, composed of A3 and four 50 kΩ resistors.
The purpose of this stage is to remove the common-mode signal from the amplified
differential signal. The transfer function of the AD8226 is
VOUT = G(VIN
? VIN?)
VREF where:
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the AD8226, which can
be calculated by referring to Table 7 or by using the following gain equation:
RG=
49.4kΩG?1
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Table 7. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω) Calculated Gain 49.9 k 1.990 12.4 k 4.984 5.49
k 9.998 2.61 k 19.93 1.00 k 50.40
G=1
49.4kΩRG
The
AD8226
defaults
to
G
=
1
when
no
gain
resistor
is
used.
The
tolerancehttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ce and gain drift of
the RG resistor should be added to the AD8226 specifications to determine the total
gain accu-racy of the system. When the gain resistor is not used, gain error and gain
drift are minimal.
If a gain of 5 is required and minimal gain drift is important, consider using the
AD8227. The AD8227 has a default gain of 5 that is set with internal resistors. Because
all resistors are internal, the gain drift is extremely low (
Rev. A | Page 19 of 28
AD8226
VCM?VCM
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REFERENCE TERMINAL
The output voltage of the AD8226 is developed with respect to the potential on the
reference terminal. This is useful when the output signal needs to be offset to a
precise midsupply level. For example, a voltage source can be tied to the REF pin
to level-shift the output so that the AD8226 can drive a single-supply ADC. The REF
pin
is
protected
with
ESD
diodes
and
shhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ceould not exceed either
VS or ?VS by more than 0.3 V.
For the best performance, source impedance to the REF terminal should be kept below
2 Ω. As shown in Figure 58,
the reference terminal, REF, is at one end of a 50 kΩ
resistor. Additional impedance at the REF terminal adds to this 50 kΩ resistor and
results in amplification of the signal connected to the positive input. The
amplification from the additional RREF can be computed by 2(50 kΩ
RREF)/(100 kΩ
RREF).
is unaffected.
Only the positive signal path is amplified; the negative path
This uneven amplification degrades CMRR.
INCORRECT
CORRECT
(V)(G)
>?VS V?LIMIT (1) 2
(V)(G)
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(VDIFF)(G)
VCM VREF
2Table 8. Input Voltage Range Constants for Various Temperatures
?LIMIT ?40°C ?0.55 V
V
LIMIT
25°C ?0.35 V
0.8
V
85°C ?0.15 V
0.7
125°C ?0.05 V
V
0.65
V
0.6
V://www.wendangwang.com/doc/b26aead8710c46420b4b74cear
VREF_LIMIT 1.3 V 1.15 V 1.05 V 0.9 V
Performance Across Temperature
The common-mode input range shifts upward with temper-ature. At cold temperatures,
the part requires extra headroom from the positive supply, and operation near the
negative supply has more margin. Conversely, hot temperatures require less headroom
from the positive supply, but are the worst-case conditions for input voltages near
the negative supply.
0Recommendation for Best Performance
Figure 59. Driving the Reference Pin
INPUT VOLTAGE RANGE
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Figure 9 through Figure 15 and Figure 18 show the allowable common-mode input voltage
ranges for various output voltages and supply voltages. The 3-op-amp architecture
of the AD8226 applies gain in the first stage before removing common-mode voltage
with the difference amplifier stage. Internal nodes between the first and second
stages (Node 1 and Node 2http://www.wendangwang.com/doc/b26aead8710c46420b4b74ce in
Figure 58) experience a combination of a gained signal, a common-mode signal, and
a diode drop. This combined signal can be limited by the voltage supplies even when
the individual input and output signals are not limited.
For most applications, Figure 9 through Figure 15 and Figure 18 provide sufficient
information to achieve a good design. For applications where a more detailed
understanding is needed, Equation 1 to Equation 3 can be used to understand how the
gain (G), common-mode input voltage (VCM), differential input voltage (VDIFF), and
reference voltage (VREF) interact. The values for the constants, V?LIMIT, V LIMIT,
and VREF_LIMIT, are shown in Table 8. These three formulas, along with the input and
output range specifications in Table 2 and Table 3, set the operating boundaries of
the part.
A typical part functions up to the boundaries described in this section. However,
for
best
designihttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ceng
performance,
with
a
few
hundred millivolts extra margin is recommended. As signals approach the boundary,
internal transistors begin to saturate, which can affect frequency and linearity
performance.
If the application requirements exceed the boundaries, one solution
is to apply less gain with the AD8226, and then apply additional gain later in the
signal chain. Another option is to use the pin-compatible AD8227.
LAYOUT
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To ensure optimum performance of the AD8226 at the PCB level, care must be taken in
the design of the board layout.
to aid in
The AD8226 pins are arranged in a logical manner
this task.
–INRGRG IN VSVOUTREF
(Not to Scale)
07036-005
–VS
Figure 60. Pinout Diagram
Rev. A | Page 20 of 28
AD8226
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8226 must have a return path to ground. When the
souhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cerce,
such
as
a
thermocouple, cannot provide a return current path, one should be created, as shown
in Figure 62.
INCORRECT
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VS
Common-Mode Rejection Ratio Over Frequency
Poor layout can cause some of the common-mode signals to be converted to differential
signals before reaching the in-amp. Such conversions occur when one input path has
a frequency response that is different from the other. To keep CMRR across frequency
high, the input source impedance and capacitance of each path should be closely
matched. Additional source resistance in the input path (for example, for input
protection) should be placed close to the in-amp inputs, which minimizes their
interaction with parasitic capacitance from the PCB traces. Parasitic capacitance
at the gain-setting pins can also affect CMRR over frequency. If the board design
has a component
at the gain-setting pins (for example, a switch or jumper), the
phttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ceart should be chosen so
that the parasitic capacitance is as small as possible.
CORRECT
–V
S
TRANSFORMER
–VS
TRANSFORMER
Power Supplies
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A stable dc voltage should be used to power the instrumentation amplifier. Note that
noise on the supply pins can adversely affect performance. For more information, see
the PSRR performance curves in Figure 23 and Figure 24.
A 0.1 μF capacitor should be placed as close as possible to each supply pin. As shown
in Figure 61, a 10 μF tantalum capacitor can be used farther away from the part.
In most cases, it can be shared by other precision integrated circuits.
–V
S
THERMOCOUPLE
VS
THERMOCOUPLE
AD8226
C
f
HIGH-PASS
REF
07036-007
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–VS
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Fhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ceigure
62.
Creating
an
IBIAS Path
Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground
References
The output voltage of the AD8226 is developed with respect to the potential on the
reference terminal. Care should be taken to tie REF to the appropriate local ground.
Rev. A | Page 21 of 28
AD8226
07036-008
INPUT PROTECTION
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The AD8226 has very robust inputs and typically does not
need additional input
protection. Input voltages can be up to 40 V from the opposite supply rail. For example,
with a
5 V positive supply and a ?8 V negative supply, the part can safely withstand
voltages from ?35 V to 32 V. Unlike some other instrumentation amplifiers, the part
can handle large differen-tial input voltages even when the part is in high gain.
Figure 16, Figure 17, Figure 19, and Figure 20 show the behavior of the part under
overvolhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cetage conditions.
The rest of the AD8226 terminals should be kept within the supplies. All terminals
of the AD8226 are protected against ESD.
For applications where the AD8226
encounters voltages beyond the allowed limits, external current-limiting resistors
and low-leakage diode clamps such as the BAV199L, the FJH1100s, or the SP720 should
be used.
Figure 63. RFI Suppression
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in applications having
strong RF signals. The disturbance can appear as a small dc offset voltage. High
frequency signals can be filtered with a low-pass RC network placed at the input of
the instru-mentation amplifier, as shown in Figure 63. The filter limits the input
signal bandwidth according to the following relationship:
CD affects the difference signal and CC affects the common-mode signal. Values of
R ahttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cend CC should be chosen to
minimize RFI. Mismatch between the R × CC at the positive input and the R × CC at
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the negative input degrades the CMRR of the AD8226. By using a value of CD that is
one magnitude larger than CC, the effect of the mismatch is reduced and performance
is improved.
FilterFrequencyDIFF=FilterFrequencyCM=where CD ≥ 10 CC.
1
2πR(2CD CC)
1
2πRCC
Rev. A | Page 22 of 28
AD8226
Tips for Best Differential Output Performance
For best ac performance, an op amp with at least a 2 MHz gain bandwidth and a 1 V/μs
slew rate is recommended. Good choices for op amps are the AD8641, AD8515, and AD820.
Keep trace lengths from the resistors to the inverting terminal of the op amp as short
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as possible. Excessive capacitance at this node can cause the circuit to be unstable.
If
capacitance
cannot
be
avoided,
ushttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cee lower value resistors.
For best linearity and ac performance, a minimum positive supply voltage ( VS) is
required. Table 9 shows the minimum supply voltage required for optimum performance.
In this mode, VCM_MAX indicates the maximum common-mode voltage expected at the input
of the AD8226.
Table 9. Minimum Positive Supply Voltage
Less than ?10°C
VBIAS)/2
VS > (VCM_MAX
1.25 V More than 25°C
VBIAS)/2
1.4 V ?10°C to 25°C
VS > (VCM_MAX
VBIAS)/2
VS > (VCM_MAX
1.1 V
APPLICATIONS INFORMATION
DIFFERENTIAL DRIVE
RECOMMENDED OPAMPS:AD8515,AD8641,AD820.RECOMMENDED RVALUES: 5k? to 20k?.
07036-009
Figure 64. Differential Output Using an Op Amp
Figure 64 shows how to configure the AD8226 for differ- ential output.
The differential output is set by the following equation:
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VDIFF_OUT
=
VOUT
?
VOUT?
=
Gain
×
(VIN
?
VIN?)
Thttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cehe common-mode output is
set by the following equation:
VCM_OUT = (VOUT
? VOUT?)/2= VBIAS
The advantage of this circuit is that the dc differential accuracy depends on the
AD8226, not on the op amp or the resistors. In addition, this circuit takes advantage
of the precise control that the AD8226 has of its output voltage relative to the
reference voltage. Although the dc performance and resistor matching of the op amp
affect the dc common-mode output accuracy, such errors are likely to be rejected by
the next device in the signal chain and therefore typically have little effect on
overall system accuracy.
Rev. A | Page 23 of 28
AD8226
Option 1 shows the minimum configuration required to drive
a charge-sampling ADC.
The capacitor provides charge to the ADC sampling capacitor while the resistor shields
the AD8226 from the capacitance. To keep the AD8226 stable, the RC time
conhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cestant of the resistor
and capacitor needs to stay above 5 μs. This circuit is mainly useful for lower
frequency signals. Option 2 shows a circuit for driving higher speed signals. It uses
a precision op amp (AD8616) with relatively high bandwidth and output drive. This
amplifier can drive a resistor and capacitor with
a much higher time constant and
is therefore suited for higher frequency applications.
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07036-010
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8226 make it an excellent
candidate for performing bridge measure-ments. The bridge can be connected directly
to the inputs of the
amplifier (see Figure 65).
Figure 65. Precision Strain Gage
DRIVING AN ADC
Figure 66 shows several methods for driving an ADC. The
ADuC7026 microcontroller was chosen for this example because it contains ADCs with
an
unbuffered,
charge-sahttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cempling
architecture that is typical of most modern ADCs. This type of architecture typically
requires an RC buffer stage between the ADC and amplifier to work correctly.
Option 3 is useful for applications where the AD8226 needs to run off a large voltage
supply but drive a single-supply ADC.
In normal operation, the AD8226 output stays
within the ADC range, and the AD8616 simply buffers it. However, in a fault condition,
the output of the AD8226 may go outside the supply range of both the AD8616 and the
ADC. This is not an issue in the circuit, however, because the 10 kΩ resistor between
the two amplifiers limits the current into the AD8616 to a safe level.
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OPTION 1: DRIVING LOW FREQUENCYSIGNALS
07036-065
Figure 66. Driving an ADC
Rev. A | Page 24 of 28
AD8226
OUTLINE DIMENSIONS
0.95PLANE
0.230.08
0.10
://www.wendangwang.com/doc/b26aead8710c46420b4b74cerCOMPLIANT TO JEDEC STANDARDS
MO-187-AA
Figure 67. 8-Lead Mini Small Outline Package [MSOP]
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(RM-8)
Dimensions shown in millimeters
0.25 (0.0098)0.10 (0.0040)COPLANARITY
0.10
0.17 (0.0067)
COMPLIANTTO JEDEC STANDARDS MS-012-AA
CONTROLLING
DIMENSIONSARE
IN
MILLIMETERS;
INCH
DIMENSIONS(INPARENTHESES)ARE
ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLYANDARE NOTAPPROPRIATE FOR USE
IN DESIGN.
012407-A
Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
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ORDERING GUIDE
Package Branding
1
AD8226ARMZ?40°C to
125°C 8-Lead MSOP RM-8 Y18 AD8226ARMZ-RL1?40°C to
125°C
8-Lead MSOP, 13" Tape and Reel RM-8 Y18
1
AD8226ARMZ-R7?40°C
to
125°C
8-Lead
MSOP,
7"
Tape
and
Reel
RMhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74ce-8 Y18 AD8226ARZ1?40°C
to
125°C 8-Lead SOIC_N R-8
AD8226ARZ-RL1?40°C to
125°C 8-Lead SOIC_N, 13" Tape
and Reel R-8
1
AD8226ARZ-R7?40°C to
to
125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8226BRMZ1?40°C
125°C 8-Lead MSOP RM-8 Y19
1
AD8226BRMZ-RL?40°C to
AD8226BRMZ-R71?40°C to
125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y19
125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y19
1
AD8226BRZ?40°C to
125°C 8-Lead SOIC_N R-8
AD8226BRZ-RL1?40°C to
125°C 8-Lead
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SOIC_N, 13" Tape and Reel R-8
1
AD8226BRZ-R7?40°C to
125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
1
Z = RoHS Compliant Part.
Rev. A | Page 25 of 28
AD8226
NOTES
Rev. A | Page 26 of 28
AD8226
NOTES
Rev. A | Page 27 of 28
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AD8226
NOTES
?2009 Analog Devices, Inhttp://www.wendangwang.com/doc/b26aead8710c46420b4b74cec.
All rights reserved. Trademarks and
registered trademarks are the property of their
respective owners.
D07036-0-7/09(A)
Rev. A | Page 28 of 28
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