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Lecture Notes on Photonics and Optoelectronics Vol. 1, No. 1, June 2013
Anew Square-Root Circuit Using Short Channel
MOSFETs with Compensation for Error
Resulting from Carrier Mobility Reduction
Munir A. AL-Absi and Ibrahim A. As-Sabban
Electrical Engineering Department, KFUPM, Dhahran, Saudi Arabia
E-mail: mkulaib@kfupm.edu.sa
Abstract—This paper presents a new current-mode
use of resistor to compensate for the errors of the
voltage term that is added to the MTL loop and this
will increase the silicon area of the circuit. A novel
higher precision square-root circuit was proposed in [8].
The design suffers from the errors caused by carrier
mobility reduction.
In this work, a new approach to compensate for the
errors due to carrier mobility reduction in square root
circuit employing MOSFETsTranslinear Loop (MTL)
is proposed.In section II, the proposed circuit is
presented. Simulation results and discussion are
presented in section III. Section IV concludes the paper.
square rooter circuit using 0.18m CMOS technology.
The design is based on MOSFETs translinear principle in
strong inversion and minimizes the second order effects
caused by carrier mobility reduction in short channel
MOSFETs. Tanner simulation tool is used to confirm the
functionality of the design. 
Index Terms—short channel MOSFETs, second order
effects, carrier mobility reduction, square root
I. INTRODUCTION
As the transistor is scaled down, second order effects
become more important and require modifications to
the MOS models or a way to compensate for the errors
due to these effects. The main effects that can be
compensated for are the channel length modulation,
body effect and the carrier mobility reduction. At large
gate-source voltage, the high electric field developed
between the gate and the channel confines the charge
carrier to a narrower region below the oxide-silicon
interface, leading to more carrier scattering and hence
lower mobility. Since scaling has substantially deviated
from the constant-field scenario, small-geometry
devices experience significant mobility degradation.
Manycompensation techniques in OTA based
circuits arereported in the literature [1-5]. There is no
much done to compensate for the error generated by
the carrier mobility reductionin the current-mode
circuits employing MOS trans-linear loop. Reference
[6] proposed a technique to reduce the error of the
output current caused by mobility reduction. The
drawbacks to this circuit are that, this method needs a
control voltage to work properly. Also, changes in
VDS of this transistor cause variations in the resistance
value which can affect the functionality of the circuit.
In [7] a squarer/divider circuit is proposed considering
second order effects caused by carrier mobility
reduction. This design is has a higher precision and
smaller chip area. The drawbacks of this design are the
II. PROPOSED CIRCUIT
The proposed square root circuit diagram is shown
in Figure 1. With reference to the figure, the input can
be applied Via M6 as Ix or via M9 asIy . If the input
current is negative, use Ix as the input and Iy as a bias
current and vice versa.
Using MTL in transistors M1, M2, M3 and M4 to
get:
V
V
V
V
SG1 SG2
SG3
SG4
If the mobility reduction is taken into consideration,
the MOS drain current is given by:
I
D


2
0
VGS  VTH 2

V
1   V
TH
GS
(2)
Where,  is a fitting parameter and  is the aspect
ratio of transistor.
The gate-to source potential can be written as:
V

GS
Manuscript received December 22, 2012; revised January 25,
2013; accepted February 14, 2013.
©2013 Engineering and Technology Publishing
doi: 10.12720/lnpo.1.1.6-8
(1)
6
I 
D


2I
D

V
TH
(3)
Lecture Notes on Photonics and Optoelectronics Vol. 1, No. 1, June 2013
VDD
M6
M5
Ix
Ix
M1
M7
I4
M4
Ix
M16
I3=I4
I3
M2
Iy
Iy
M3
Iy
Ix
M11
M12
M8
M10
M9
1/2Iy
(Ix+Iy)
Io=√(Ix*Iy)
1/2Ix
IIout=√(Ix*Iy)
M15
M13
M14
M17
M18
Figure 1. Proposed Current-mode Square root Circuit
Combining Eq (1) and (3) to get:
I 
D1 1

1

2I
D1

1

I

D2 2

2I

D2

2

I

D3 3

2
2I

D3

3

I
3

D4 4

I out 
2I

D4

4
(4)


2I y


I x


2I x

I 
D3

2

2I
D3

2
I 
D4
2
2I

D4
Iout = K Ix
III. SIMULATION RESULTS
Since the drain current of transistors M3 and M4 are
the same, Eq. 5 can be expressed by;
 I x  I y  1  2I x  2I y   2 2I D3  1 2 I D3 

If


we
force
the
following
The proposed circuit was simulated using Tanner
tools in 0.18µm CMOS technology. The circuit is
operating form 1.3V power supply. The aspect ratio of
all transistors used for simulation is listed in Table 1.
The input current Iy=5µA and Ixis swept from 0 to
20µA. It is clear from the plot that simulated and
calculated results are in a good agreement.
(6)
condition
I x  I y   2  2 I D3  , then

I D3  I x  I y
TABLE I. TRANSISTOR ASPECT RATIOS
(7)
W/L
Combining Eq. 6and 7 to get:
 2I x 

1
2I y



1
2 I
D3

(8)
Squaring both side of Eq. 8, then
2I x  I y   4 I x  I y  4 I D 3
(9)
Eq. 9 can be written as:
I D3 
Ix  Iy
2
Subtracting the term

Ix  Iy
Ix  Iy
2
(µm)
W/L(µm)
W/L (µm)
M1 2/0.18
M7
2/0.18
M13
2/0.18
M2 2/0.18
M8
1/0.18
M14
1/0.18
M3 4/0.18
M9
2/0.18
M15
1/0.18
M4 4/0.18
M10
2/0.18
M5 2/0.18
M11
2/0.18
M16
4/0.18
M6 2/0.18
M12
2/0.18
M17
1/1
M18
1/1
(10)
Simulation and calculated results are shown in
Figure 2. It is clear from the plot that simulated and
calculated results are in a good agreement.
from Eq. 10, the
output current can be expressed as:
©2013 Engineering and Technology Publishing
(12)
It is clear that Eq.12 implements square root circuit.
(5)
2
(11)
With reference to Figure 1, the circuit can be used to
produce the square root of the current going out, using
Ix as input or going in using Iy as an input.
If the current Iy is kept fixed, Eq.11 can be written as
4
Where IDi is the drain current for the transistor
i. Assuming that β1= β2= β and β3= β4= 2β and θ1=
θ2= θ3= θ4= θ , then Eq. 4 can be written as:
I y
Ix  Iy
7
Lecture Notes on Photonics and Optoelectronics Vol. 1, No. 1, June 2013
IV. CONCLUSION
3
A new square rooter circuit using short channel
MOSFETs in strong inversion is developed. The circuit
is based on MTL with mobility carrier reduction is
minimized. The functionality of the proposed circuit
was confirmed using Tanner simulation tool.
2
ACKNOWLEDGEMENTS
1
The authors would like to thank KFUPM for
supporting this research.
Output current , Iout (uA)
5
4
Simulated
0
0
2
4
6
8
Calculated
10
Input current , IX (uA)
Conventional
12
14
16
18
REFERENCES
20
[1]
Figure 2.Simulated and calculated results for the square root circuit.
[2]
A. Temperature and Mismatch Analysis
The circuit was simulated for temperature variation.
The temperature was varied from 25 to 75C.
[3]
[4]
[5]
[6]
[7]
Figure 3.Simulation results for temperature variation/
Simulation against mismatch in channel length was
carried out for MOSFETS forming the translinear loop.
Simulation result is shown in Figure 4. It is evident
from the figure that the variation is in acceptable range.
[8]
E. Ibaragi, A. Hyogo, and K. Seikine, “A novel CMOS OTA
free from mobility degradation effect,” in Proc. IEEE Asia
Pacific Conference of Circuit and Systems, 1998, pp. 241-244.
S. H. Yang et al., “A novel CMOS operational
transconductance amplifier based on a mobility compensation
technique,” IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 52,
no. 1, pp. 37-42, Jan. 2005.
T. Y. Lo and C. C. Hung, “A 1-V 50 MHz pseudodifferentialOTAwith compensation of the mobility reduction,”
IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 54, no. 12, pp.
1047-1051, Dec. 2007.
K. Tanno, D. Ide, K. Nishimura, H. Tanaka, and H. Tamura,
“Highly-linear CMOS OTA with compensation of mobility
reduction,” in Proc. IEEE Asia Pacific Conference on Circuits
and Systems, 2008, pp. 810-813.
S. Sengupta, “Adaptively biased linear transconductor,” IEEE
Trans. On Circuits and Systems–I: Regular Papers, vol. 52, no.
11, pp. 2369-2375, Nov. 2005.
S. Menekay, R. C. Tarcan, and H. Kuntman “Novel high
precision current-mode multiplier/divider,” in Proc.
International Conference on Electrical and Electronics
Engineering, (ELECO-2007), 2007, pp. 5-9.
M. Tavassoli, A. Khoei, and Kh. Hadidi, “High-precision–
linear loop-based squarer/divider circuit free from mobility
reduction,” in Proc. 19th Iranian Conference on Electrical
Engineering, 2011.
S. Menekay, R. C. Tarcan, and H. Kuntman, “The Secondorder low-pass filter design with a novel higher precision
square-root circuit,” Journal of Electrical and Electroni
Engineering, vol. 7, no.1, 2007, pp. 323-729.
Munir Al-Absi was born in Yemen. He received his M.Sc. from
KFUPM in 1987 and Ph.D in 2001. His research interests include
CMSO analog computational circuits, Current mode circuits.
Ibrahim As-Sabban was born in Yemen. He is currently a graduate
student at KFUPM working in CMOS analog computational circuit
using MOSFETs in strong inversion.
Figure 4. Simulation result for mismatch analysis.
©2013 Engineering and Technology Publishing
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