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Fast Transient Power Converter Using Switched
Current Conversion
Laurence McGarry
Advanced Engineering Technology Manager
Hong Kong & China
Astec Power
A Division of Emerson Network Power.
Abstract: Next generation microprocessors continue to require power
supplies capable of supporting fast transient loading. Conventional
approaches to solving the fast transient issue focus on the use of
interleaved buck converters. This approach is fundamentally limited
due to the presence of the output inductance, limiting the converter
response to a load transient. This paper introduces a novel switched
current converter. The converter will switch current to the load or to
ground depending on the load transient requirement, providing a
theoretically infinite transient response. The research investigates the
practical limitations of the converter topology, using simulation to
evaluate and optimize the system design. Finally, simulation models
and results are presented and suggestions for further design
improvements are discussed.
Common Industry Trends
• Intel CPU requirement for VRM
Intel CPU voltage and Current Roadmap
Processor trends well documented :
ƒ Higher Current Requirements
ƒ Lower Voltage Processors, tighter regulation range
ƒ Higher Frequencies
ƒ Faster Transient Response
Conventional Industry Approaches
ƒ Standard approach to resolving the challenge is to use interleaved Buck
converters
ƒ Response time inherently limited by the presence of the output inductor
ƒ Problem compounded by interconnect and PCB parasitics
ƒ Continued silicon integration, drive to higher frequencies and possibly an
increased number of phases will continue to be a trend regardless of the
architecture utilized
ƒ Switched Current Techniques offer an alternative approach
ƒ An infinite transient response possible, in theory at least
2
Conventional Buck Converter
2
Volterra 300A/uS Module 369mm
Switched Current Concepts
ƒ Currents are switched to the load or to the return path
ƒ Parallel switching Current Paths are utilized
ƒ Transient can be supported in the time that it takes to turn the FET On/Off
ƒ When output current follows processor demand current, significant
reduction in output capacitance can be observed
ƒ The constant current source is derived from a Buck Converter driving a
matrix Transformer configuration
2
Constant Current Source
ƒ Front end Buck converter provides the constant current source
ƒ Push Pull Converter operating at 100% duty using a ‘Matrix transformer’
provides the input to the current switches at the load side
ƒ Matrix Transformer: series (primary), parallel (secondary) ferrite cells
forming individual isolation for each phase
ƒ LHS source is constant current
and could be remote from the
end application.
ƒ RHS Switches could be colocated with the processor to
reduce interconnect parasitics
and enhance transient response
2
System Overview and Simulation Model
ƒ Front End Buck Converter providing constant current source
ƒ Push-Pull Converter with Matrix Transformer provides constant current
parallel paths
ƒ Output Current switches; switching current to the load in response to
transients or to ground
ƒ Simulation model: 3 Stage Conversion
-12V input to 1V, 100A output
- 10 parallel switching paths
Constant Current Source Buck Converter
ƒ Buck Constant Current Converter
ƒ Simple Hysteretic Control Implemented
5.6u IC =10.5
D R V1s
Q3
irf 7822
Iout
L2
R8
irf 7822
12
V15
X1
10k
Q4
Ireturn
MAX473
10m
R 15
3.3k
1K R 13
R 14
+5Vc c
10k
R1
1
U 17
H C 74D
U 19
m ax 961
Vc c
IN +
NQ
IN SH D N
Q
Q SET D
Vref H igh
GN D
LE
QN
R ST
E3
1
E4
10k
R2
+5Vc c
U 18
m ax 961
Vc c
IN +
NQ
IN Vref Low
Q
SH D N
GN D
LE
ƒ No Output Capacitance
ƒ 2 level Threshold Control
10A-11A
ƒ Synch Rectification is used to
reduce power loss
ƒ Switching Frequency Varies
according to the Buck Output
voltage, reaching maximum
while Voutput Buck=0.5Vin
ƒ Voltage on the output of the
Buck is n X Vo
- Where n is the number of switches
turned to the load
Constant Current Source Buck Converter(cont)
Simulation Results light load
Simulation Results Light load
•
•
•
•
•
Buck output voltage=0.5V
Output current =10.87A
Switching Duty cycle=5.55%
Switching Frequency=110kHz
Current ripple =694mA
Simulation Results Full load
Simulation Results Full load
•
•
•
•
•
Buck output voltage=11V
Output current =10.69A
Switching Duty cycle=93%
Switching Frequency=133kHz
Current ripple =760mA
Constant Current Source Buck Converter(cont)
Simulation Results Dynamic load
•
•
•
Output voltage slew rate=46V/us
Output current =10.8A
Current ripple =828mA
Simulation result on dynamic load
fs vs Vo Curve
L=5.6uH, ∆I=1A.
6 10
Input Buck Frequency Variation
• The highest frequency =518kHz
(output voltage =5.5V)
• All components are ideal
5
5
4 . 10
fs ( Vo )
5
2 . 10
0
0
5
10
Vo
Push Pull Converter
B ra nc h 1
2n
2n
TX 1
L5
L2
Q1
irf 6603
10.5
I1
irf540ns
4.7n
C1
Q3
2k
R 1 irf 540ns
2n
2n
L4
L3
4.7n
C3
Q4
D1
IDEA L
D3
IDEA L
2k
R7
Q2
irf 6603
ƒ Fixed Duty Cycle of 50%
ƒ Leakage Inductance causes
increased voltage stress on
Primary FETs
ƒ Gate Drive Timing for Primary
FETs and secondary Synchronous
Rectification FETs is critical
Push Pull Converter – Matrix Transformer
ƒ Matrix Transformer Structure:
Core Size 11.8 X 6 X 4 mm
ƒ Coupling Coefficients:
Pri-Sec 0.996, Pri-Pri 0.994, Sec-Sec 0.994
ƒ Important for the Matrix Transformer cells and SRs to be in close proximity
ƒ Staggered placement of the Matrix Cells on either side of the PCB
facilitates optimum layout
Matrix Transformer Modeling
Magnetising Inductance
Leakage S-P
Leakage S-S
Leakage P-P
Equivalent R
In The Middle
2.07uH
2.72nH
7.11nH
10.94nH
1.38mOhm
Primary R
Secondary R
Magnetising Current
Core Loss
Standalone With Primary Termination
0.5mm
4.5mm
2.07uH
3.27nH
8.04nH
7.79nH
11.61nH
1.41mOhm
2.08mOhm
0.476mOhm
0.934mOhm
1.063A
0.375W
Push Pull Converter – Drive Signal Timing
Primary Gate Drive Overlapping
G1
G2
ƒ First, overlapping drive is considered to
avoid breaking current source path
ƒ Two primary windings are shorted during
the period of overlapping and a current
gap occurs
ƒ Spike across the drain source is caused
by the energy stored in leakage inductor
Primary Gate Drive Non-Overlapping
ƒ Non-overlapping avoids shorting the
primary winding
ƒ Spike on drain is caused by the current
transient
ƒ Current gap occurs during this period as
the two primary FETs are off
ƒ Non-overlapping gate drive is used. Adjusting dead time optimizes the current gap
ƒ Device capacitance is sufficient to provide current continuity during commutation
Push Pull Converter – Drive Signal Timing (cont)
ƒ Reverse Recovery of Synch Rect. for non-overlapping
ƒ Simulation waveform under
100mOhm Load. 100nS primary
deadtime, 150nS leading SR
delay. 60nS SR trailing edge
delay.
ƒ Note reverse recover current
during SR off time
ƒ The spike due to reverse
recover current depends on the
parasitic inductance of trace on
PCB
Switched Current Converter
1m
Q1
irf 6601_1
I1
irf 6601_1
Q2
10
R2
D3
IDEAL
10
R3
D2
IDEAL
OUT N1
OUT N1
ARB1
ARB2
Vo
4.7u
C1
Vcc
U1
max962
VSp
Qout_p
Qout_n
VINp
VINn
VSn
Gnd
Vref 1
ƒ Output Capacitance is necessary but smaller
ƒ Voltage feedback
ƒ Current supplied to the load is determined by voltage drop on the
capacitor
ƒ Delay of control loop requires a larger capacitance
ƒ ESR and ESL of Output Capacitance is critical to the step control
ƒ Gate drive timing stops current to load before short current to ground
Switched Current Converter(cont)
Simulation on dynamic load = 400A/us
Simulation condition:
ƒ Load current is changed from 5A
to 95A (blue)
ƒ Load current slew rate = 400A/us
Simulation result:
ƒ Load voltage is varied from
1.022V to 0.975V (light green)
ƒ The red line Ic is the current waveform before output capacitance
ƒ The light green line is the buck output current waveform
Switched Current Converter(cont)
Simulation on dynamic load = 1000A/us
Simulation condition:
ƒ Load current is changed from 5A
to 95A (blue)
ƒ Load current slew rate = 1000A/us
Simulation result:
ƒ Load voltage is varied from
1.022V to 0.975V (light green)
Switched Current Converter(cont)
Simulation on dynamic load = 2000A/us
Simulation condition:
ƒ Load current is changed from 5A
to 95A (blue)
ƒ Load current slew rate = 2000A/us
Simulation result:
ƒ Load voltage is varied from
1.022V to 0.975V (light green)
ƒ The Slew Rate has no obvious effect on the Output Voltage Deviation
Switched Current Converter(cont)
Modeling The Interconnect:
ƒ All the previous simulations include the parasitics associated with
the a representative system interconnect
ƒ The simulations do not include PCB parasitics and depend on
component simulation accuracy
VRM
current output
180u
C1
100p
40u
L1
R5
300u
R3
VRM
output cap
560u
C5
300u
R6
inter-connection
decoupling
capacitors
Future
Processor
Model
System Measurements – Actual results
ƒ Load changed from 0-50%, 5 phases switching
ƒ Early results indicate that the 927A/uS can be achieved on rise time
ƒ Optimisation continues…..
System Power Budget
Buck Converter
item
output choke
Mosfet High side
Mosfet low side
sense Resistance
Driver IC
total power losses
components
EE18
IRF7822
IRF7822
0.01OHM
ISL6605
output power
Efficiency
Push Pull and
Switch Current
Total
full load 100A 1V
power losses(W)
0.281
2.463
0.127
1
0.04
3.911
114.754
96.70%
RCD
transformer
Martrix
PP Mosfet
STP75NF75
SYN Mosfet
IRF6618
Switch current Mosfe IRF6618
total power losses
power loss
load power
total input power
Efficiency
light load 10A 1V
power losses(W)
0.281
1.693
0.744
1
0.04
3.758
23.154
86.04%
2.5
5.3
1.804
2.81
2.34
14.754
0.9
5.3
1.804
2.81
2.34
13.154
18.665
100
118.665
84.27%
16.912
10
26.912
37.16%
ƒ System Power Budget indicates that the overall efficiency ~ 84%
ƒ ~2-3% Lower than a conventional VRM due to the 3-Stage Topology
System Assembly
ƒ 6 layer PCB 75mm X 25 mm
ƒ Assembly height 13.6mm
ƒ Matrix transformer divided between the top and bottom sides
ƒ Rectifier FETs close to Matrix Transformer
Summary and Conclusions:
ƒ This paper introduces the concepts of switched current conversion as a
possible alternative to common industry approaches to Fast transient
requirements
ƒ The converter consists of 3 Stages: Buck Current source, Push Pull
converter employing a matrix transformer and the switched current output
ƒ Simulation results indicate that the topology can meet very fast transient
requirements limited only by parasitics and sensing delays
ƒ Reduces overall system capacitance
ƒ Transient response could be further enhanced by moving the switched
current section to the load application
ƒ Silicon integration to reduce complexity and component count
ƒ Advent of flexible Digital control systems to reduce the number of phases,
reduce complexity and improve efficiency
Reference Material
1)
Edward Herbert, “ Switched-current Power Converter”, 2003
2)
Edward Herbert, “ Voltage Control for Switched-current Power Converter”,
3)
Edward Herbert, “ Fast Transition Power Control for Processors Using Switched
Current and Switched Charge ”
Edward Herbert, “ Input Characteristics and Waveforms for Switched-Current Power
Converters”
4)