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WORST-CASE NOISE AREA PREDICTION OF
ON-CHIP POWER DISTRIBUTION NETWORK
Xiang Zhang1, Jingwei Lu2, Yang Liu3 and Chung-Kuan Cheng1,2
1
ECE Dept., University of California, San Diego, CA, USA
2
CSE Dept., University of California, San Diego , CA, USA
3
Institute of Electronic CAD, Xidian University, Xi’an, China
2014-06-01
1
EXECUTIVE SUMMARY

Problem: Previous works focus on the worst-peak
droop to sign off PDN.




Worst-peak noise ≠ Worst timing (delay)
Our goal: To predict a PDN noise for better timing
sign off.
Observation: The noise area of PDN => Behavior of
circuit delay
Case study: Design the worst-case PDN noise area
Provide analytical solution for a lumped PDN model
 Design an algorithm for general PDN cases


Results: Worst-area noise introduces 1.8% additional
propagation delay compared to worst-peak noise from
our empirical validation under a complete PDN path.
2
POWER DISTRIBUTION NETWORK (PDN)

Power supply noise
Resistive IR drop
 Inductive Ldi/dt noise


PDN model
3
MOTIVATION

Performance sensitivity on PDN voltage drop
Increased signal delay [Saint-Laurent’04] [Jiang’99]
 Clock jitter [Pialis’03]

4
Delay vs supply voltage(courtesy of [Saint-Laurent’04])
PDN NOISE AREA VS DELAY

Delay is measured under a modified C432 of ISCAS85 circuit in 130nm node
5
PROBLEM FORMULATION

PDN Characterization

Impulse Response h(t)
• Input to PDN system
• Transient load current demand
i(t)
• Assumption:
• All on-die loads lumped into
a single load
• Total current is bounded

Voltage Noise:
6
PROBLEM FORMULATION

Worst-caset peak noise [Hu et al @ SLIP2009]

v peak (t )   h( )i (t   )d
0

𝑖 𝜏 = 1 when ℎ 𝑡 − 𝜏 ≥ 0
𝑖 𝜏 = 0 when ℎ 𝑡 − 𝜏 < 0
Voltage Noise Area




where the worst-current 𝑖𝑤 (𝑡):
Integral within sliding window
Window size T corresponds to
one clock cycle
Defined as 𝐴(𝑖, 𝑡), a function of
input current 𝑖(𝑡)
Worst-case optimization

Design of current 𝑖𝑤 (𝑡) and voltage drop 𝑣𝑤 (𝑡)

Achieve maximum noise area Aw and interval [𝑡𝑤 − T, 𝑡𝑤 )

Can be solved by polynomial-time method
7
PROBLEM SIMPLIFICATION

Binary-valued worst current


Current decomposition


Can be proved that 𝑖𝑤(𝑡) only switches between 0 and 1
𝑖(𝑡) equals the superposition of
a series of step inputs
Single step input & response

Step response 𝑉𝑠 (𝑡)

Integrate into ramp response 𝑅𝑠 (𝑡)

Noise area function 𝐴𝑠 (𝑡)
8
SIMPLIFIED PROBLEM FORMULATION
A linear-constrained linear optimization problem
 Input

A power network system with impulse response h(t)
 Given window size T


Output
Window location 𝑡𝑤
 Phase delay of step inputs, 𝑡𝑘 ∈ {𝑡0 , 𝑡1 , … }


Objective


Maximum noise area Aw within [𝑡𝑤 − 𝑇, 𝑡𝑤 )
Constraints

𝑖𝑤 (𝑡) = 0 𝑂𝑅 1, t is (0, +∞)
9
CASE STUDY: RLC TANK MODEL

Impedance Profile:
, where


Step Response 𝑉𝑠 :


Assume Q>0.5, system is underdamped
where
Ramp Response 𝑅𝑠 :

where
10
WORST NOISE AREA PREDICTION FOR RLC
TANK

Given a window size T, worst-area noise is
𝑡𝑤 is set to a relatively large value when ℎ(𝑡) ≈ 0.
 𝐴𝑠 is


𝑡𝑘 is the time when local peaks/valleys of 𝐴𝑠 occur.

Solved by setting 𝐴′𝑠 𝑡 = 0, since 𝐴𝑠 is piecewise-defined func.
 Case 1 (𝑡 ≤ 𝑇): 𝑡𝑘 is the solution of
, i.e.

Case 2 (𝑡 > 𝑇):
11
where 𝑋 = 𝑒 𝛼𝑇 𝐴𝑐𝑜𝑠 𝛽𝑇 + 𝐵𝑠𝑖𝑛 𝛽𝑇 , 𝑌 = 𝑒 𝛼𝑇 𝐴𝑠𝑖𝑛 𝛽𝑇 + 𝐵𝑐𝑜𝑠 𝛽𝑇 .
CASE STUDY: WORST NOISE AREA
PREDICTION FOR GENERAL PDN CASES

Real PDN structure is complicated
 Consists of multiple frequency components
 Develop algorithm
 Algorithm design for general cases
– Given window size T and arbitrary impulse response ℎ(𝑡)
– Determine the phase delay 𝑡𝑘 of each step input 𝑠𝑘 𝑡
– Constructs 𝑖𝑤 (𝑡) by superposing 𝑠𝑘 (𝑡)
– Maximum noise 𝐴𝑤 is achieved
12
INTUITION

Align all 𝐴𝑠 𝑡 − 𝑡𝑘 together to generate 𝑖𝑤 (𝑡)
Select one point from 𝐴𝑠 (𝑡) to determine the phase
delay 𝑡𝑘
 Maximize (+) 𝑠𝑘 (𝑡) by choosing peak points
 Minimize (-) 𝑠𝑘 (𝑡) by choosing valley points
 Determine 𝑡𝑤 as the last peak of 𝐴𝑠 (𝑡).


𝐴𝑤 = sum of all peaks- sum of all valleys
13
ALGORITHM DESIGN

Given ℎ(𝑡) & 𝑇


Generate 𝑉𝑠(𝑡), 𝑅𝑠(𝑡) and 𝐴𝑠(𝑡)


Step responses and its
transformation
Extract all peaks and valleys of
𝐴𝑠(𝑡)


Impulse response and window
size
Linear scanning on 𝐴𝑠(𝑡)
Calculate each peak-to-valley
distance
Determine phase delay 𝑡𝑘
accordingly
 Determine 𝑠𝑘 (t) by 𝑡𝑘 and its sign
(±)


Construct 𝑖𝑤 (𝑡)

adding up all 𝑠𝑘(𝑡) together
14
COMPLEXITY ANALYSIS

Our algorithm consists of finite operations
Step response transformation
 Linear scan for peaks & valleys extraction
 Worst-case current construction


Overall complexity is O(n)
Finite amount of operations
 Each operation consumes no larger than linear
runtime

15
EXPERIMENTAL DESIGN AND RESULTS

Setup:







Matlab R2013a
HSPICE D-2013.03-SP1
Cadence Allegro Sigrity Power SI 16.6
Ansoft Q3D 12.0
ISCAS85 circuit under 0.13um cell lib
Intel i7 Qual-Core 3.4GHz w/16GB PCDDR3
PDN test cases
Single RLC tank
 Cascaded RLC tanks
 A complete PDN path extracted from industrial design

16
WORST-PEAK AND WORST-AREA NOISE OF
A SINGLE RLC TANK CASE
10mΩ 250pH
33nF i(t)
12mΩ
Nominal Vdd= 1V,
T=17ns
Both load current
activities stop at
𝑡𝑤 = 5us
17
WORST-AREA AND WORST-PEAK NOISE OF
MULTI-STAGE CASCADED RLC TANKS

Circuit Model

Three Cases
Case I can be approximated to three single
RLC tanks:
18
WORST-AREA AND WORST-PEAK NOISES
OF MULTI-STAGE CASCADED RLC TANKS
Compare the worst-case noise predcition from the
analytical solution approximations from RLC
tank decomposition vs solution of Algorithm 1
 𝑇 = 10𝑛𝑠 for 𝐴𝑤


Prediction Error (on average) :
7.75% for the worst-peak noise
 12.3% for the worst-area noise

19
WORST-PEAK AND WORST-AREA NOISE OF
A COMPLETE PDN PATH

Impedance Profile:
20
WORST-PEAK AND WORST-AREA NOISE OF
A COMPLETE PDN PATH

Worst-peak and worst-area noise solved by Alg. 1

𝑇 = 12.5𝑛𝑠, 𝑉𝑑𝑑 = 1.15𝑉
21
DELAY MEASUREMENT OF A COMPLETE
PDN PATH

Send input pulse every 100ps and record delay of the datapath at the output
port of C432 (ISCAS85) case

Compare the delay under worst-peak and worst-area noise

Results:
22
CONCLUSIONS

Problem: Previous works focus on the worst-peak
droop to sign off PDN.




Worst-peak noise ≠ Worst timing (delay)
Our goal: To predict a PDN noise for better timing
sign off.
Observation: The noise area of PDN => Behavior of
circuit delay
Case study: Design the worst-case PDN noise area
Provide analytical solution for a lumped PDN model
 Design an algorithm for general PDN cases


Results: Worst-area noise introduces 1.8% additional
propagation delay compared to worst-peak noise from
our empirical validation under a complete PDN path.
23
Q&A
24
25
DELAY MEASUREMENT OF SINGLE RLC
TANK CASE

Send input pulse every 100ps and record delay of the
datapath at the output port of C432 (ISCAS85) case
26