Download Logic Switches Operating at the Minimum Energy of Computing

2015 IEEE Computer Society Annual Symposium on VLSI
Logic Switches Operating at the Minimum
Energy of Computing
Francesco Orfei, Luca Gammaitoni
NiPS Lab, Dept. of Physics, University of Perugia
Via A. Pascoli 1, 06123 Perugia, Italy
francesco.orfei@nipslab.org
must dissipate KBT ln(2) because it reduces the information
between the input and the output. However only the theoretical
prediction on the heat produced by resetting one bit of
information (Landauer principle) has been confirmed
experimentally [7], while there is still no proof that a NAND
gates generates KBT ln(2) of heat per bit of information lost
during computation. Additionally, it has been recently
suggested that the energy efficiency of the bit resetting
operation can be improved allowing a finite error probability
during operation [3, 8]. This has never been tested neither as a
fundamental physical limit, nor as a technological shortcut
available with the off-the-shelf logic gates.
Abstract— In modern computers information is processed
through binary switches, usually realized with transistors, i.e.
microelectronic devices. Thus binary switches represent a
paradigmatic example of "small scale physical systems"
employed in the processing of information. In the last forty years
the semiconductor industry has been driven by its ability to scale
down the size of the CMOS devices, to increase computing
capability and reducing the power dissipated in heat. Thus we
assisted to a continuous reduction in the supply voltage and
electrical noise induced errors became an important issue to take
into account for the performance of the device. Here we discuss
the relationship between the energy required by an advanced
ultra low power logic gate and the associated error rate at
different operating frequencies.
Logic switches are the fundamental component of each
logic gate. Logic gates can be used in any digital circuit,
computer, portable equipment or telecommunication device.
Portable equipment requires a very small package to fit in its
compact slim casing, and a low supply voltage to meet the
requirements of CPUs and MCUs, as well as low power
consumption to extend battery life. For example, smart phones,
as well as many other portable devices, become more complex,
more features are offered to the user, but more power is
consumed by systems in both active and standby mode.
Consequently, selecting low-power devices for portable
electronics imposes new challenges in the areas of core
voltage, energy management, and battery lifetime. Increasing
microprocessor complexity generally increases power
consumption and migration to low-power CMOS logic
achieves the lowest power consumption in both dynamic and
static mode situations.
Keywords—binary switches; CMOS; logic gate; scaling; error
rate; energy; computing; noise
I.
INTRODUCTION
Computation is energy demanding: this statement is clear to
whoever uses an electronic device, but has deeper implications
than expected. As a matter of fact, the energy issue is at the
moment one of the major limitation in the development of both
small autonomous wireless sensor nodes and large scale
supercomputers. In the former case, computing devices are
intended to be small (micro-nano scales) and self powered
through some energy harvesting techniques [1-2]. The main
problem is that micro and nano energy harvesters are not yet
able to efficiently power off-the-shelf sensors, processors and
wireless transmitters: they generally require power at mW
scale, but these harvester are able to convert μWs of power, not
enough. In the latter case, each processor of a supercomputer
requires enormous amount of energy, because power, the
product of current and voltage, has to be fed into the system to
properly operate it. Consequently the heat produced while
operating must be removed from the chip to preserve
functionality. From these two different examples it's clear that
lowering energy consumption in computing devices is then one
of the main goals of ICT industry [3].
In this work a NAND gate has been tested to evaluate its
performances at variable bit rate when its supply voltage is
decreased below the minimum voltage specified by the
producer. In this way it has been possible to identify the
minimum supply voltage before error rate rises up to a non
negligible limit. Reducing the supply voltage has an impact on
the total power dissipation, but it is important to understand the
quantitative correlation between the power saving and the error
rate when the device is under-powered. It has been also
investigated the behavior of the error generation trying to find
if it can be predicted or not.
On the other hand, this may be limited or forbidden by
physics: from the early work of Landauer [4], it is well
understood that resetting one bit of information with no error
requires a minimum heat production of KBT ln(2), where T is
the temperature of the bit-encoding device and KB is
Boltzmann constant. This seems to apply to nowadays logic
gates too. In an extensive interpretation of the Landauer
principle, some authors [5-6] claim that a NAND logic gate
978-1-4799-8719-1/15 $31.00 © 2015 IEEE
DOI 10.1109/ISVLSI.2015.39
II.
ENERGY DISSIPATION IN LOGIC SWITCHES
Energy consumption during computation has become a
matter of strategic importance for modern ICT and its impact
on future society. In the last forty years the progress of the
semiconductor industry has been driven by its ability to cost
274
effectively scale down the size of the CMOS-FET [9] switches
while increasing their density. This has been accompanied by a
continuing increase in energy consumption and heat generation
up to a point where the power dissipated in heat during
computation has become a serious limitation [10, 11]. An
information processor can be seen as a computing engine that
transforms incoming energy flow into useful work and also
produces some heat [3, 12]. It has been shown that information
processing is intimately related to energy management
(“information is physical”)[4]. The ultimate limit on the
minimum energy per switch resetting is set at KBT ln2
(approximately 10-21 J at room temperature) [4, 13] while there
is no fundamental limit associated with the switching operation
per sè [3]. This limit is known to be the Shannon-von
Neumann-Landauer (SNL) limit. As Landauer argued, this
minimum amount cannot be reduced to zero if some
information is discarded (erased) during the computation
process. The reason is directly linked to thermodynamics: if
erasing information decreases the overall entropy of the
system, this cannot be done without dissipating heat of at least
KBT ln2 J per bit erased [4, 13]. It is important to review the
sources of energy consumption in state of the art ICT systems,
since this may offer insights for possible directions to improve
their energy efficiency.
[3]. A switch event is a change from an initial condition to a
final condition. During this change the exchanges of energy
and entropy need to be accounted for. If the switch is thermally
isolated from the external environment, then there can be no
transfer of heat. If it is possible to suppose for a moment that a
switching event can be performed without any work from
outside, then the only balance that needs to be taken into
account is the change in entropy. This change is measured by
the change in the macroscopic configuration of the switch. If
the change is from state open to state close, then there is only
one initial configuration and one final configuration. There is
therefore no net change in the number of configurations and
thus no change in entropy according to Boltzmann. If now a
status change is imposed to put the switch into a close (or
open, same reasoning) condition, the number of configurations
is halved and thus there is a change in entropy according to
Boltzmann given by the (1):
ܵ௙ െ ܵ௜ ൌ ݇஻ ሺŽ ͳ െ Ž ʹሻ ൌ െ݇஻ Ž ʹ
(1)
where kB is Boltzmann’s constant (1.38 × 10–23 J/K).
The change in entropy is associated with a change in heat via
the relation (2):
(2)
ܶ݀ܵ ൒ ݀ܳ
A. Fundamental limits
An ICT device can be seen as a machine [14, 15] that
receives in input information and energy (in the form of work),
and after processing them gives information and energy (in the
form of heat) as output. A traditional thermal machine is a
device that processes energy. More precisely it transforms
energy in the form of heat into work for industrial applications.
An ICT device is a slightly more complex machine because it
processes energy and information at the same time. More
specifically, it inputs a certain amount of data and some energy
in the form of work and outputs a reduced amount of
information and the same quantity of energy, although in the
form of heat. In modern computers the information is
processed via networks of logic gates. In a real computer, the
logic gate function is realized by some physical components.
The bit value is represented by some physical entity (signal)
such as an electric current or voltage, light intensity, magnetic
field etc. Such signal inputs to the logic gate device and go
through a transformation to represent at the output the desired
bit value. The minimum energy to operate a physical switch
can be reduced to zero provided that the quantity of
information associated to the physical entropy in the switch is
not decreased during the switch transformation. This condition
has been pointed out initially by John von Neumann in a
lecture in 1949 [6] and subsequently focused by R. Landauer
[7] and extended, sometimes loosing the connection between
physical entropy and quantity of information, by C. H. Bennet
[13].
B. Practical limits
Two components determine the power consumption in a
CMOS circuit: static power consumption and dynamic power
consumption [16]. The first is proportional to the current
flowing into the device as a consequence of leakages; the
second one is related to the current required during switching.
CMOS devices have very low static power consumption
because parasitic diodes are reverse biased and only their
leakage currents contribute to static power consumption. The
leakage current (Ilkg) of the diode is described by the following
equation (3):
௤௏
‫ܫ‬௟௞௚ ൌ ‫ܫ‬ௌ ൬݁ ௞் െ ͳ൰
(3)
Where:
IS = reverse saturation current (A)
V = diode voltage (V)
k = Boltzmann’s constant (1.38 × 10–23 J/K)
q = electronic charge (1.602 × 10–19 C)
T = temperature (K)
Static power consumption is the product of the device
leakage current and the supply voltage. Total static power
consumption PS can be obtained as:
ܲௌ ൌ ෍ሺŽ‡ƒƒ‰‡ …—””‡–ሻ ȉ ሺ•—’’Ž›˜‘Ž–ƒ‰‡ሻ
(4)
Dynamic power consumption is due to the current that
flows only when the transistors are switching from one logic
state to another. This is a result of the current required to
charge the internal nodes (switching current) plus the through
current (current that flows from the supply voltage VCC to
GND when the p-channel transistor and n-channel transistor
turn on briefly at the same time during the logic transition).
The frequency at which the device is switching, plus the rise
The reason is the following: the switch is a macroscopic
apparatus composed by many elementary parts (atoms) and
thus can be considered a thermodynamic system approximately
at equilibrium with the environment. This implies that its
transformations are subjected to the laws of thermodynamics
275
and fall times of the input signal, as well as the internal nodes
of the device, have a direct effect on the duraation of the current
spike. For fast input transition rates, the throough current of the
gate is negligible compared to the switchingg current. For this
reason, the dynamic supply current is governned by the internal
capacitance of the IC and the charge and diischarge current of
the load capacitance. If we consider the energy
e
required to
drive an inverter’s output high and low, thhis is the same of
loading and discharging a capacitor CL throuugh a resistor RL. It
is possible to evaluate the energy stored andd dissipated in the
resistor and capacitor as:
ୖై
IV.
(5)
଴
‫ܥ‬௅ ܸ ଶ
(6)
ʹ
The energy dissipated for one switch opeeration is given by
the equation:
‫ܧ‬஼ಽ ൌ
‫ܧ‬ௌௐ ൌ ‫ܧ‬ோಽ ൅ ‫ܧ‬஼ಽ ൌ ‫ܥ‬௅ ܸ ଶ ൌ ‫ܥ‬௣ௗ ܸ ଶ
(7)
Considering NSW working at the frequuency fI, transient
power consumption can be calculated using equation
e
(8).
୘ ൌ ȉ ୮ୢ ȉ େେ ଶ ȉ ˆ୍ ȉ ୗ୛
୛
(8)
where:
PT = transient power consumption (W)
= activity factor, =1 for a square waave switching and
<0.5 in typical digital circuits
A Flip-Flop type D has been used to sample and hold the
output of the comparator for thhe entire time interval of one bit.
It is clocked by the main system’s clock, an arbitrary
programmable signal generatorr. To minimize the propagation
delay difference between thhe two signal paths to the
comparator, two GUT boards are
a used in parallel and the same
signal generator produces thee bit sequence to evaluate the
performances of the NAND gates.
g
At the output from these
boards the signals are time aligned except for a small time
interval due to the different propagation delay of the two
NAND. At lower voltage supplly the propagation delay rises. A
SN74AUP1G00 is the NAND gate
g used for the experiment.
Cpd = dynamic power-dissipation capacitaance (F)
VCC = supply voltage (V)
fI = input signal frequency (Hz)
NSW = number of bits switching
III.
EXPERIIMENTAL SETUP
Aim of the experiment is to
t obtain a relationship between
the bit error-rate and the powerr consumed by a logic device, a
SN74AUP1G00 [17] two inputts single NAND gate from Texas
Instruments, under several tesst conditions. The experimental
setup is composed by a stabble voltage supply, a variable
voltage supply, a signal geneerator, a digital comparator, a
temperature sensor, some curreent to voltage converters and an
asynchronous counter. The bloock diagram of the experimental
setup is depicted in Fig. 1. Tw
wo of GUT boards (GUT Gate
Under Test board) are used inn parallel. In the first one, the
NAND gate is always powered at the nominal voltage of 3.3 V:
in this way no errors are expeccted during its working time. In
the other board, instead, the NAND
N
gate is powered from a
variable voltage power supplyy. In this way it is possible to
control the supply voltage of thhe logic device to the minimum
value of 0.4 V. An EX-OR is used
u
as bit comparator to detect
errors. At its input the output signals of the GUT boards are
presented. When the two inputss are not equal, the output of the
comparator goes to the logicc level “1”. This is the error
detection condition requireed during this experiment.
Unfortunately the output of thee EX-OR gate is asynchronous,
or in other words, it changes sttate as soon as the inputs change
state and a synchronization ciircuitry is required to correctly
measure the number of errors.
ଶ
୲
ୖଶ ሺ–ሻ
୐ ଶ
ቀି
ቁ
ൌ න ై †– ൌ
න ൤‡ ୖైେై ൨ †–– ൌ
୐
ʹ
୐
଴
interesting to make a test to exxperimentally obtain the relation
between the error rate and thhe energy consumption due to
voltage lowering.
THE RELATION ENERGY VERSUS ERROR RATE
In the datasheet of logic gates nothing iss written about the
relation between the energy dissipated and the
t error rate. It is
important, in fact, that each device can work without producing
unexpected or unpredictable results. It is alsoo important that the
device works demanding the minimum posssible energy. It has
been observed, discussed and demonstrateed that there is a
relation between energy and information, that the practical
amount of energy is technology dependant annd that the amount
of energy required for information proceessing is directly
proportional to the velocity of the processsing itself. Great
advancements have been made on electroonic devices, and
today's technology requires millions times less
l
energy that in
the past. But we are still quite far from
m the theoretical
Landauer's limit. What to do?
a
could be
It has been suggested that a significant advantage
reached by lowering the gate voltage. In this case it is expected
that keeping the same technology and reduciing the energy per
bit can lead to an increase of the error raate because of the
thermal noise and the barrier crossing effect. Unfortunately not
much is reported in a typical product datassheet, so it can be
Fig. 1. Block diagram of the system designed
d
for the evaluation of the error
rate.
276
VI. MEASUREMENTS AND RESULTS
AUP (advanced ultra-low-power CMOS) is one of the
lowest power families now on the market. Its operating power
supply range is extending from 0.8 V to 3.6 V, with a 3.5-ns
typical propagation delay, along with a reduced current drive
capability of 4 mA. Typical Cpd for one NAND gate
(SN74AUP1G00) is 4 pF at 3.3 V. The typical quiescent
current ICC is around 0.5 μA (0.9 μA max) when the input
voltage is equal to the supply voltage, and it increases of up to
40 μA per each gate when the input voltage is lower than the
supply voltage. The highest operating frequency is 190 MHz.
The dynamic current of the NAND gate is measured
through the voltage across a precision shunt resistor. Its value
is 10 / 0.125 W and the precision is ±0.1%. To have an
easier reading, the small voltage is amplified by a differential
amplifier: the gain of the amplifier is set to 100.
Several measurements have been performed following the
procedure previously described. Anyway a preliminary test of
the system has been conducted to check that each part was
properly working. In particular, Fig. 2 depicts the propagation
delay difference between the two channels of the GUT boards.
As it can be seen the time difference is only about 200 ps,
meaning that this will not be the source of errors, at least at low
baud rates, and the system can be correctly used to perform all
the tests on the gate. In this preliminary test all the two gate
were normally powered at 3.3 V. Fig. 3 depicts the correlation
among the dynamic current, the error rate and the voltage gap
between the two logic states at different bit rate and variable
supply voltage (0.4 V to 3.3 V). From these measurements is
possible to obtain an estimation of the overall (internal and
external load capacitance) power dissipation capacitance Ce.
V. TEST PROCEDURES
The bit rate for the tests has been chosen low enough to not
have issues with the propagation delay. This means that delays
on the two different signal paths can be neglected with respect
the bit duration. Moreover the expected delay introduced by
the under-powered gate will be much bigger than the small
difference in time between the digital signals through the two
NAND gates.
It is well known that reducing the power supply voltage
saves energy but the propagation delay generally increases.
The first measurement set is devoted to obtain the dynamic
current required by the NAND gate during its operation. A
second one, instead, is devoted to count the number of errors
of the under powered gate. The counting of the errors is
performed by a Racal-Dana 1992 Nanosecond Universal
Counter. A third measurement is required to investigate the
voltage gaps between the high (VH) and low (VL) voltage
levels of the output signal from the NAND gate. This is an
important measurement to try to understand the reason why
errors rise up.
The procedure to perform the measurement of the dynamic
currents, the errors and the voltage gaps is the following:
1. set the initial reference voltage to obtain a stable power
supply of the 0.4 V;
2. set the initial bit rate to have 0.5 Mbps and apply the bit
sequence to the input pin of the NAND gate;
3. check the voltage supply to be the desired one;
4. read the current to voltage converter output, the number
of errors and the voltage gap;
5. increase the bit rate;
6. repeat the point 3 to 5 till the bitrate arrives to 5 Mbps;
7. increase the voltage reference of a small amount (10 to
25 mV);
8. repeat the steps from the point 2 to the point 7 till to
arrive to the maximum level of the supply voltage of
3.3 V.
The bit rates used for the measurements are: 0.5 Mbps, 1
Mbps, 1.5 Mbps, 2 Mbps, 3 Mbps, 4 Mbps and 5 Mbps. All the
tests have been performed at 25°C.
Considering a dynamic current of 200 μA at 2.5 V and 5
Mbps, the value of Ce is given by the equation (9) and it is in
good agreement with the predictions.
‫ܫ‬஼஼
(9)
ൎ ͳ͸‫ܨ݌‬
ܸ஼஼ ȉ ݂௢
As it can be seen, when the supply voltage is greater than
0.8 V no errors are measurable, as expected. Moreover, the
curves of the error rates and of the voltage gap converge on the
right part of the graphs, meaning that the system is working
properly.
‫ܥ‬௘ ൌ
More interesting are the left parts of the graphs, as
depicted in Fig. 4, Fig. 5 and Fig. 7: these figures show the
dynamic currents, the error rates and the voltage gaps
respectively at different bit rates and when the supply voltage
ranges between 0.4 V and 0.8 V: we were interested to
investigate the error probability in extreme low power
operating condition. Fig. 4 depicts the dynamic current of the
NAND gate at different bit rates as function of the supply
voltage. As it can be noted, there are points where the slope of
the curves changes.
Fig. 2. Propagation delay difference between the two channels at 3.3 V: red
line represents the signal coming from the variable voltage power supply,
green line represents the constant 3.3 V powered signal. The time difference is
200 ps (it has been measured in the point where the signals reach 1.5 V).
277
Fig. 3. Results of the measurements of the dynamic cuurrent, of the error rate
and of the voltage gap between the high and low leveel of the output of the
NAND gate.
Fig. 4. Dynamic currents of the NAND
D gate. The plot shows the static current
Iq and the dynamic currents in the 0.4 V to 0.8 V voltage range at different bit
rates. The "" marked line is an exponnential curve passing for the point where
the dynamic current slope changes signnificantly.
These points are few tens of mV highher than the point
where the error rates rise (see Fig. 5). These points can be
interpolated by and exponential curve ass function of the
supply voltage: this means that higher bit raates require higher
supply voltages.
(10)
‫ܫ‬௖ ൌ ͲǤͲͺ͹͹Ͷ݁ ሺଵ଴Ǥ଺ସȉ௏಴಴ ሻ
f
of the bit
Fig. 5 depicts the error rates curves as function
rate and the supply voltage. As it can be easily
e
seen, all the
curves can be approximated by an erfc funcction defined as in
the (11):
݁‫݂ܿݎ‬ሺܸ஼஼ ሻ ൌ
ʹ
ξߨ
ஶ
మ
න ݁ ି௧ ݀‫ݐ‬
(11)
௏಴಴
Fig. 5. Plot of the error rate measurem
ment as function of the supply voltage,
from 0.4 V to 0.8 V, at different bit rates. The dashed lines are the
corresponding complementary erfc funnctions.
All these error functions are parallel to eaach other and they
appear to be only translated: it was possiible to obtain the
translation coefficients values ்ܸ௥ and they are
a depicted in Fig.
6 as function of the bit rate: they are linearlyy dependant by the
bit rate BR:
(12)
்ܸ௥ ൌ ͲǤͲ͵ͳͷ ȉ ‫ܤ‬ோ ൅ ͲǤͶʹͺ
Same considerations can bee done for the 3 Mbps curve. At
0.525 V its probability of errror is raising rapidly and its
voltage separation is approxim
mately 0.28 V. Let’s choose a
point where the errors are closse to zero, for example 0.54 V.
At this supply voltage the voltage separation is approximately
35 % lower, it is close to 0.35 V. Considering that at this
voltage level and at this bit ratte the logic gate is still working,
the power saving on the outputt signal is approximately 58%.
Fig. 7 depicts the voltage differences betw
ween the high and
low level of the output of the NAND gate as function of the
supply voltage and at different bitrates. As it can be seen, all
w
the device is
the curves converge to the supply voltage when
working correctly, it means for supply voltage over the corner
voltage VC discussed before. As it is triviall to imagine, they
converge again when the supply voltage goees to zero: no more
energy. In the middle of these two convergeences, they exhibit
a “s” shape trend and some consideratioons can be done
correlating these curves with the probabiliity of error. First
consider the voltage separation at 5 Mbps annd its value in the
point where the error probability rises rapidly,
r
it means
approximately at 0.58 V of voltage supply. From
F
the graphs of
Fig. 7 this value can be found to be approoximately 0.35 V.
Anyway at this level of voltage the errrors are no more
negligible. Instead, at a supply voltage of 0.59 V the error
probability is close to zero and the voltage separation
s
is close
to 0.4 V. Compared to the supply voltage, it is approximately
32% lower. In terms of power of the outpuut signal from the
NAND gate, this means a power saving of approximately
54%, and the device is still working correctlyy.
CLUSIONS
VII. CONC
In this work a NAND loogic gate has been studied to
investigate its error-rate behaviior in its nominal voltage supply
range and in under-powering conditions. The dynamic current,
v
separation between the
the error probability and the voltage
logic states of the output have
h
been studied and some
remarkable features can be noteed:
• The dynamic current ICC(VCC) as a function of the
supply voltage VCC, groows linearly for VCC > VT1 , a
threshold value that assumes different values for
different bit rates BR, VT1
T = VT1(BR).
• For VCC < VT1(BR) the
t
ICC(VCC) decreases almost
exponentially with an exponent
e
that is approximately
the same for different biit rates.
278
Fig. 8. Double well potential energy of
o a hypothetical particle in a particular
bistable system. The height of the barriier decreases when the distance between
the equilibrium positions decreases: at the lower limit of zero height the
equilibrium positions are no more distiinguishable.
Fig. 6. Plot of the translation coefficients used to approoximate the probability
of error measurements with an erfc distribution as funcction of the bit rate. In
blue the coefficient used, in red their linear interpolationn.
REFER
RENCES
[1]
[2]
[3]
[4]
[5]
[6]
Fig. 7. Voltage gaps of the output voltage of the NAND
D gate between the high
and low state as function of the supply voltage at diffferent bit rates, in the
supply voltage range 0.4 V to 0.8 V.
[7]
• The error probability Pe(VCC) as a function of the
supply voltage VCC, decreases rapidlly for VCC > VT2 .
VT2 assumes different values for diffe
ferent bit rates BR,
VT2 = VT2(BR)
• For VCC < VT2(BR) the error probabillity Pe(VCC) = 1, it
stays maximum regardless the valuue of the supply
voltage, i.e. the response is totally ranndom.
• VT1(BR) is not necessarily equal to VT2(BR).
• VT1(BR) and VT2(BR) grows approxim
mated proportional
with BR.
[8]
[9]
[10]
[11]
[12]
Based on these considerations, it is possible to propose a
phenomenological model for ICC(VCC) and Pe(VCC). First it can
be noted the absence of a step-like behavior for VCC = VT2, i.e.:
Pe(VCC) = 0 for VCC > VT2 and Pe(VCC) = 1 foor VCC < VT2 . This
is not the case here, and Pe(VCC) looks like an
a exponential, far
enough from a step-like behavior. This seem
ms to indicate the
role played by the voltage/threshold flucctuations and the
device failure appears to be a stochastic phenomenon
p
other
than a deterministic event. A more realistic model of the two
states of equilibrium can thus be proposedd by introducing a
bistable potential, where the distance betweeen the two wells
and the height of the barrier is supply voltagge dependent, as it
can be seen in Fig. 8.
[13]
[14]
[15]
[16]
[17]
279
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3.0
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