A single ended 6T SRAM cell design for ultra-low
A Simple Drain Current Model for MOS Transistors with the Lorentz
A Simple and Unambiguous Definition of Threshold Voltage and Its
A Self-aligned Gate Definition Process with Submicron Gaps
A selection of research topics in semiconductor physics at the Cavendish Laboratories
A Secure Dynamically Programmable Gate Array Based on
A Scalable, Timing-Safe, Network-on-Chip Architecture